//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// The confidential and proprietary information contained in this file may     
// only be used by a person authorised under and to the extent permitted       
// by a subsisting licensing agreement from ARM Limited.                       
//                                                                             
//            (C) COPYRIGHT 2005-2013 ARM Limited.
//                ALL RIGHTS RESERVED                                          
//                                                                             
// This entire notice must be reproduced on all copies of this file            
// and copies of this file may only be made by a person if such person is      
// permitted to do so under the terms of a subsisting license agreement        
// from ARM Limited.                                                           
//                                                                             
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Top-Level Verilog file is auto-generated by AMBA Designer ADr3p4-00rel0-build-0086
//                                                                             
// Stitcher: generic_stitcher_core v3.1, built on Sep 18 2013
//                                                                             
// Filename: nic400_cd_clk_peri_100m_ysyx_rv32.v
// Created : Mon May 27 20:11:34 2024                            
//                                                                             
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Generated with Validator version0.1


//-----------------------------------------------------------------------------
// Module Declaration nic400_cd_clk_peri_100m_ysyx_rv32
//-----------------------------------------------------------------------------

module nic400_cd_clk_peri_100m_ysyx_rv32 (
  
// Instance: u_amib_perip0_gp_apb4, Port: gpio_slv_apb4

  paddr_gpio_slv_apb4,
  pwdata_gpio_slv_apb4,
  pwrite_gpio_slv_apb4,
  pprot_gpio_slv_apb4,
  pstrb_gpio_slv_apb4,
  penable_gpio_slv_apb4,
  pselx_gpio_slv_apb4,
  prdata_gpio_slv_apb4,
  pslverr_gpio_slv_apb4,
  pready_gpio_slv_apb4,
  
// Instance: u_amib_perip0_gp_apb4, Port: i2c_slv_apb4

  paddr_i2c_slv_apb4,
  pwdata_i2c_slv_apb4,
  pwrite_i2c_slv_apb4,
  pprot_i2c_slv_apb4,
  pstrb_i2c_slv_apb4,
  penable_i2c_slv_apb4,
  pselx_i2c_slv_apb4,
  prdata_i2c_slv_apb4,
  pslverr_i2c_slv_apb4,
  pready_i2c_slv_apb4,
  
// Instance: u_amib_perip0_gp_apb4, Port: pwm0_slv_apb4

  paddr_pwm0_slv_apb4,
  pwdata_pwm0_slv_apb4,
  pwrite_pwm0_slv_apb4,
  pprot_pwm0_slv_apb4,
  pstrb_pwm0_slv_apb4,
  penable_pwm0_slv_apb4,
  pselx_pwm0_slv_apb4,
  prdata_pwm0_slv_apb4,
  pslverr_pwm0_slv_apb4,
  pready_pwm0_slv_apb4,
  
// Instance: u_amib_perip0_gp_apb4, Port: pwm1_slv_apb4

  paddr_pwm1_slv_apb4,
  pwdata_pwm1_slv_apb4,
  pwrite_pwm1_slv_apb4,
  pprot_pwm1_slv_apb4,
  pstrb_pwm1_slv_apb4,
  penable_pwm1_slv_apb4,
  pselx_pwm1_slv_apb4,
  prdata_pwm1_slv_apb4,
  pslverr_pwm1_slv_apb4,
  pready_pwm1_slv_apb4,
  
// Instance: u_amib_perip0_gp_apb4, Port: pwm2_slv_apb4

  paddr_pwm2_slv_apb4,
  pwdata_pwm2_slv_apb4,
  pwrite_pwm2_slv_apb4,
  pprot_pwm2_slv_apb4,
  pstrb_pwm2_slv_apb4,
  penable_pwm2_slv_apb4,
  pselx_pwm2_slv_apb4,
  prdata_pwm2_slv_apb4,
  pslverr_pwm2_slv_apb4,
  pready_pwm2_slv_apb4,
  
// Instance: u_amib_perip0_gp_apb4, Port: qspi_slv_apb4

  paddr_qspi_slv_apb4,
  pwdata_qspi_slv_apb4,
  pwrite_qspi_slv_apb4,
  pprot_qspi_slv_apb4,
  pstrb_qspi_slv_apb4,
  penable_qspi_slv_apb4,
  pselx_qspi_slv_apb4,
  prdata_qspi_slv_apb4,
  pslverr_qspi_slv_apb4,
  pready_qspi_slv_apb4,
  
// Instance: u_amib_perip0_gp_apb4, Port: rtc_slv_apb4

  paddr_rtc_slv_apb4,
  pwdata_rtc_slv_apb4,
  pwrite_rtc_slv_apb4,
  pprot_rtc_slv_apb4,
  pstrb_rtc_slv_apb4,
  penable_rtc_slv_apb4,
  pselx_rtc_slv_apb4,
  prdata_rtc_slv_apb4,
  pslverr_rtc_slv_apb4,
  pready_rtc_slv_apb4,
  
// Instance: u_amib_perip0_gp_apb4, Port: uart_slv_apb4

  paddr_uart_slv_apb4,
  pwdata_uart_slv_apb4,
  pwrite_uart_slv_apb4,
  pprot_uart_slv_apb4,
  pstrb_uart_slv_apb4,
  penable_uart_slv_apb4,
  pselx_uart_slv_apb4,
  prdata_uart_slv_apb4,
  pslverr_uart_slv_apb4,
  pready_uart_slv_apb4,
  
// Instance: u_amib_perip0_gp_apb4, Port: vgalcd_slv_apb4

  paddr_vgalcd_slv_apb4,
  pwdata_vgalcd_slv_apb4,
  pwrite_vgalcd_slv_apb4,
  pprot_vgalcd_slv_apb4,
  pstrb_vgalcd_slv_apb4,
  penable_vgalcd_slv_apb4,
  pselx_vgalcd_slv_apb4,
  prdata_vgalcd_slv_apb4,
  pslverr_vgalcd_slv_apb4,
  pready_vgalcd_slv_apb4,
  
// Instance: u_amib_perip0_gp_apb4, Port: wdg_slv_apb4

  paddr_wdg_slv_apb4,
  pwdata_wdg_slv_apb4,
  pwrite_wdg_slv_apb4,
  pprot_wdg_slv_apb4,
  pstrb_wdg_slv_apb4,
  penable_wdg_slv_apb4,
  pselx_wdg_slv_apb4,
  prdata_wdg_slv_apb4,
  pslverr_wdg_slv_apb4,
  pready_wdg_slv_apb4,
  
// Instance: u_amib_perip1_gp_apb4, Port: archinfo_slv_apb4

  paddr_archinfo_slv_apb4,
  pwdata_archinfo_slv_apb4,
  pwrite_archinfo_slv_apb4,
  pprot_archinfo_slv_apb4,
  pstrb_archinfo_slv_apb4,
  penable_archinfo_slv_apb4,
  pselx_archinfo_slv_apb4,
  prdata_archinfo_slv_apb4,
  pslverr_archinfo_slv_apb4,
  pready_archinfo_slv_apb4,
  
// Instance: u_amib_perip1_gp_apb4, Port: crc_slv_apb4

  paddr_crc_slv_apb4,
  pwdata_crc_slv_apb4,
  pwrite_crc_slv_apb4,
  pprot_crc_slv_apb4,
  pstrb_crc_slv_apb4,
  penable_crc_slv_apb4,
  pselx_crc_slv_apb4,
  prdata_crc_slv_apb4,
  pslverr_crc_slv_apb4,
  pready_crc_slv_apb4,
  
// Instance: u_amib_perip1_gp_apb4, Port: ps2_slv_apb4

  paddr_ps2_slv_apb4,
  pwdata_ps2_slv_apb4,
  pwrite_ps2_slv_apb4,
  pprot_ps2_slv_apb4,
  pstrb_ps2_slv_apb4,
  penable_ps2_slv_apb4,
  pselx_ps2_slv_apb4,
  prdata_ps2_slv_apb4,
  pslverr_ps2_slv_apb4,
  pready_ps2_slv_apb4,
  
// Instance: u_amib_perip1_gp_apb4, Port: psram_slv_apb4

  paddr_psram_slv_apb4,
  pwdata_psram_slv_apb4,
  pwrite_psram_slv_apb4,
  pprot_psram_slv_apb4,
  pstrb_psram_slv_apb4,
  penable_psram_slv_apb4,
  pselx_psram_slv_apb4,
  prdata_psram_slv_apb4,
  pslverr_psram_slv_apb4,
  pready_psram_slv_apb4,
  
// Instance: u_amib_perip1_gp_apb4, Port: rng_slv_apb4

  paddr_rng_slv_apb4,
  pwdata_rng_slv_apb4,
  pwrite_rng_slv_apb4,
  pprot_rng_slv_apb4,
  pstrb_rng_slv_apb4,
  penable_rng_slv_apb4,
  pselx_rng_slv_apb4,
  prdata_rng_slv_apb4,
  pslverr_rng_slv_apb4,
  pready_rng_slv_apb4,
  
// Instance: u_amib_perip1_gp_apb4, Port: spi0_slv_apb4

  paddr_spi0_slv_apb4,
  pwdata_spi0_slv_apb4,
  pwrite_spi0_slv_apb4,
  pprot_spi0_slv_apb4,
  pstrb_spi0_slv_apb4,
  penable_spi0_slv_apb4,
  pselx_spi0_slv_apb4,
  prdata_spi0_slv_apb4,
  pslverr_spi0_slv_apb4,
  pready_spi0_slv_apb4,
  
// Instance: u_amib_perip1_gp_apb4, Port: spi1_slv_apb4

  paddr_spi1_slv_apb4,
  pwdata_spi1_slv_apb4,
  pwrite_spi1_slv_apb4,
  pprot_spi1_slv_apb4,
  pstrb_spi1_slv_apb4,
  penable_spi1_slv_apb4,
  pselx_spi1_slv_apb4,
  prdata_spi1_slv_apb4,
  pslverr_spi1_slv_apb4,
  pready_spi1_slv_apb4,
  
// Instance: u_amib_perip1_gp_apb4, Port: tim0_slv_apb4

  paddr_tim0_slv_apb4,
  pwdata_tim0_slv_apb4,
  pwrite_tim0_slv_apb4,
  pprot_tim0_slv_apb4,
  pstrb_tim0_slv_apb4,
  penable_tim0_slv_apb4,
  pselx_tim0_slv_apb4,
  prdata_tim0_slv_apb4,
  pslverr_tim0_slv_apb4,
  pready_tim0_slv_apb4,
  
// Instance: u_amib_perip1_gp_apb4, Port: tim1_slv_apb4

  paddr_tim1_slv_apb4,
  pwdata_tim1_slv_apb4,
  pwrite_tim1_slv_apb4,
  pprot_tim1_slv_apb4,
  pstrb_tim1_slv_apb4,
  penable_tim1_slv_apb4,
  pselx_tim1_slv_apb4,
  prdata_tim1_slv_apb4,
  pslverr_tim1_slv_apb4,
  pready_tim1_slv_apb4,
  
// Instance: u_amib_perip1_gp_apb4, Port: tim2_slv_apb4

  paddr_tim2_slv_apb4,
  pwdata_tim2_slv_apb4,
  pwrite_tim2_slv_apb4,
  pprot_tim2_slv_apb4,
  pstrb_tim2_slv_apb4,
  penable_tim2_slv_apb4,
  pselx_tim2_slv_apb4,
  prdata_tim2_slv_apb4,
  pslverr_tim2_slv_apb4,
  pready_tim2_slv_apb4,
  
// Instance: u_amib_perip1_gp_apb4, Port: tim3_slv_apb4

  paddr_tim3_slv_apb4,
  pwdata_tim3_slv_apb4,
  pwrite_tim3_slv_apb4,
  pprot_tim3_slv_apb4,
  pstrb_tim3_slv_apb4,
  penable_tim3_slv_apb4,
  pselx_tim3_slv_apb4,
  prdata_tim3_slv_apb4,
  pslverr_tim3_slv_apb4,
  pready_tim3_slv_apb4,
  
// Instance: u_amib_psram_slv_axi4, Port: psram_slv_axi4_m

  awid_psram_slv_axi4,
  awaddr_psram_slv_axi4,
  awlen_psram_slv_axi4,
  awsize_psram_slv_axi4,
  awburst_psram_slv_axi4,
  awlock_psram_slv_axi4,
  awcache_psram_slv_axi4,
  awprot_psram_slv_axi4,
  awvalid_psram_slv_axi4,
  awready_psram_slv_axi4,
  wdata_psram_slv_axi4,
  wstrb_psram_slv_axi4,
  wlast_psram_slv_axi4,
  wvalid_psram_slv_axi4,
  wready_psram_slv_axi4,
  bid_psram_slv_axi4,
  bresp_psram_slv_axi4,
  bvalid_psram_slv_axi4,
  bready_psram_slv_axi4,
  arid_psram_slv_axi4,
  araddr_psram_slv_axi4,
  arlen_psram_slv_axi4,
  arsize_psram_slv_axi4,
  arburst_psram_slv_axi4,
  arlock_psram_slv_axi4,
  arcache_psram_slv_axi4,
  arprot_psram_slv_axi4,
  arvalid_psram_slv_axi4,
  arready_psram_slv_axi4,
  rid_psram_slv_axi4,
  rdata_psram_slv_axi4,
  rresp_psram_slv_axi4,
  rlast_psram_slv_axi4,
  rvalid_psram_slv_axi4,
  rready_psram_slv_axi4,
  
// Instance: u_amib_sdram_slv_axi4, Port: sdram_slv_axi4_m

  awid_sdram_slv_axi4,
  awaddr_sdram_slv_axi4,
  awlen_sdram_slv_axi4,
  awsize_sdram_slv_axi4,
  awburst_sdram_slv_axi4,
  awlock_sdram_slv_axi4,
  awcache_sdram_slv_axi4,
  awprot_sdram_slv_axi4,
  awvalid_sdram_slv_axi4,
  awready_sdram_slv_axi4,
  wdata_sdram_slv_axi4,
  wstrb_sdram_slv_axi4,
  wlast_sdram_slv_axi4,
  wvalid_sdram_slv_axi4,
  wready_sdram_slv_axi4,
  bid_sdram_slv_axi4,
  bresp_sdram_slv_axi4,
  bvalid_sdram_slv_axi4,
  bready_sdram_slv_axi4,
  arid_sdram_slv_axi4,
  araddr_sdram_slv_axi4,
  arlen_sdram_slv_axi4,
  arsize_sdram_slv_axi4,
  arburst_sdram_slv_axi4,
  arlock_sdram_slv_axi4,
  arcache_sdram_slv_axi4,
  arprot_sdram_slv_axi4,
  arvalid_sdram_slv_axi4,
  arready_sdram_slv_axi4,
  rid_sdram_slv_axi4,
  rdata_sdram_slv_axi4,
  rresp_sdram_slv_axi4,
  rlast_sdram_slv_axi4,
  rvalid_sdram_slv_axi4,
  rready_sdram_slv_axi4,
  
// Instance: u_amib_sys_gp_apb4, Port: clint_slv_apb4

  paddr_clint_slv_apb4,
  pwdata_clint_slv_apb4,
  pwrite_clint_slv_apb4,
  pprot_clint_slv_apb4,
  pstrb_clint_slv_apb4,
  penable_clint_slv_apb4,
  pselx_clint_slv_apb4,
  prdata_clint_slv_apb4,
  pslverr_clint_slv_apb4,
  pready_clint_slv_apb4,
  
// Instance: u_amib_sys_gp_apb4, Port: plic_slv_apb4

  paddr_plic_slv_apb4,
  pwdata_plic_slv_apb4,
  pwrite_plic_slv_apb4,
  pprot_plic_slv_apb4,
  pstrb_plic_slv_apb4,
  penable_plic_slv_apb4,
  pselx_plic_slv_apb4,
  prdata_plic_slv_apb4,
  pslverr_plic_slv_apb4,
  pready_plic_slv_apb4,
  
// Instance: u_amib_sys_gp_apb4, Port: rcu_slv_apb4

  paddr_rcu_slv_apb4,
  pwdata_rcu_slv_apb4,
  pwrite_rcu_slv_apb4,
  pprot_rcu_slv_apb4,
  pstrb_rcu_slv_apb4,
  penable_rcu_slv_apb4,
  pselx_rcu_slv_apb4,
  prdata_rcu_slv_apb4,
  pslverr_rcu_slv_apb4,
  pready_rcu_slv_apb4,
  
// Instance: u_asib_vgalcd_mst_axi4, Port: vgalcd_mst_axi4_s

  awid_vgalcd_mst_axi4,
  awaddr_vgalcd_mst_axi4,
  awlen_vgalcd_mst_axi4,
  awsize_vgalcd_mst_axi4,
  awburst_vgalcd_mst_axi4,
  awlock_vgalcd_mst_axi4,
  awcache_vgalcd_mst_axi4,
  awprot_vgalcd_mst_axi4,
  awvalid_vgalcd_mst_axi4,
  awready_vgalcd_mst_axi4,
  wdata_vgalcd_mst_axi4,
  wstrb_vgalcd_mst_axi4,
  wlast_vgalcd_mst_axi4,
  wvalid_vgalcd_mst_axi4,
  wready_vgalcd_mst_axi4,
  bid_vgalcd_mst_axi4,
  bresp_vgalcd_mst_axi4,
  bvalid_vgalcd_mst_axi4,
  bready_vgalcd_mst_axi4,
  arid_vgalcd_mst_axi4,
  araddr_vgalcd_mst_axi4,
  arlen_vgalcd_mst_axi4,
  arsize_vgalcd_mst_axi4,
  arburst_vgalcd_mst_axi4,
  arlock_vgalcd_mst_axi4,
  arcache_vgalcd_mst_axi4,
  arprot_vgalcd_mst_axi4,
  arvalid_vgalcd_mst_axi4,
  arready_vgalcd_mst_axi4,
  rid_vgalcd_mst_axi4,
  rdata_vgalcd_mst_axi4,
  rresp_vgalcd_mst_axi4,
  rlast_vgalcd_mst_axi4,
  rvalid_vgalcd_mst_axi4,
  rready_vgalcd_mst_axi4,
  
// Instance: u_ib_perip0_gp_apb4_ib_m, Port: perip0_gp_apb4_ib_s_async

  a_data_perip0_gp_apb4_ib_int_async,
  a_rpntr_gry_perip0_gp_apb4_ib_int_async,
  a_rpntr_bin_perip0_gp_apb4_ib_int_async,
  a_wpntr_gry_perip0_gp_apb4_ib_int_async,
  d_data_perip0_gp_apb4_ib_int_async,
  d_rpntr_gry_perip0_gp_apb4_ib_int_async,
  d_rpntr_bin_perip0_gp_apb4_ib_int_async,
  d_wpntr_gry_perip0_gp_apb4_ib_int_async,
  w_data_perip0_gp_apb4_ib_int_async,
  w_rpntr_gry_perip0_gp_apb4_ib_int_async,
  w_rpntr_bin_perip0_gp_apb4_ib_int_async,
  w_wpntr_gry_perip0_gp_apb4_ib_int_async,
  
// Instance: u_ib_perip1_gp_apb4_ib_m, Port: perip1_gp_apb4_ib_s_async

  a_data_perip1_gp_apb4_ib_int_async,
  a_rpntr_gry_perip1_gp_apb4_ib_int_async,
  a_rpntr_bin_perip1_gp_apb4_ib_int_async,
  a_wpntr_gry_perip1_gp_apb4_ib_int_async,
  d_data_perip1_gp_apb4_ib_int_async,
  d_rpntr_gry_perip1_gp_apb4_ib_int_async,
  d_rpntr_bin_perip1_gp_apb4_ib_int_async,
  d_wpntr_gry_perip1_gp_apb4_ib_int_async,
  w_data_perip1_gp_apb4_ib_int_async,
  w_rpntr_gry_perip1_gp_apb4_ib_int_async,
  w_rpntr_bin_perip1_gp_apb4_ib_int_async,
  w_wpntr_gry_perip1_gp_apb4_ib_int_async,
  
// Instance: u_ib_psram_slv_axi4_ib_m, Port: psram_slv_axi4_ib_s_async

  aw_data_psram_slv_axi4_ib_int_async,
  aw_rpntr_gry_psram_slv_axi4_ib_int_async,
  aw_rpntr_bin_psram_slv_axi4_ib_int_async,
  aw_wpntr_gry_psram_slv_axi4_ib_int_async,
  b_data_psram_slv_axi4_ib_int_async,
  b_rpntr_gry_psram_slv_axi4_ib_int_async,
  b_rpntr_bin_psram_slv_axi4_ib_int_async,
  b_wpntr_gry_psram_slv_axi4_ib_int_async,
  ar_data_psram_slv_axi4_ib_int_async,
  ar_rpntr_gry_psram_slv_axi4_ib_int_async,
  ar_rpntr_bin_psram_slv_axi4_ib_int_async,
  ar_wpntr_gry_psram_slv_axi4_ib_int_async,
  r_data_psram_slv_axi4_ib_int_async,
  r_rpntr_gry_psram_slv_axi4_ib_int_async,
  r_rpntr_bin_psram_slv_axi4_ib_int_async,
  r_wpntr_gry_psram_slv_axi4_ib_int_async,
  w_data_psram_slv_axi4_ib_int_async,
  w_rpntr_gry_psram_slv_axi4_ib_int_async,
  w_rpntr_bin_psram_slv_axi4_ib_int_async,
  w_wpntr_gry_psram_slv_axi4_ib_int_async,
  
// Instance: u_ib_sdram_slv_axi4_ib_m, Port: sdram_slv_axi4_ib_s_async

  aw_data_sdram_slv_axi4_ib_int_async,
  aw_rpntr_gry_sdram_slv_axi4_ib_int_async,
  aw_rpntr_bin_sdram_slv_axi4_ib_int_async,
  aw_wpntr_gry_sdram_slv_axi4_ib_int_async,
  b_data_sdram_slv_axi4_ib_int_async,
  b_rpntr_gry_sdram_slv_axi4_ib_int_async,
  b_rpntr_bin_sdram_slv_axi4_ib_int_async,
  b_wpntr_gry_sdram_slv_axi4_ib_int_async,
  ar_data_sdram_slv_axi4_ib_int_async,
  ar_rpntr_gry_sdram_slv_axi4_ib_int_async,
  ar_rpntr_bin_sdram_slv_axi4_ib_int_async,
  ar_wpntr_gry_sdram_slv_axi4_ib_int_async,
  r_data_sdram_slv_axi4_ib_int_async,
  r_rpntr_gry_sdram_slv_axi4_ib_int_async,
  r_rpntr_bin_sdram_slv_axi4_ib_int_async,
  r_wpntr_gry_sdram_slv_axi4_ib_int_async,
  w_data_sdram_slv_axi4_ib_int_async,
  w_rpntr_gry_sdram_slv_axi4_ib_int_async,
  w_rpntr_bin_sdram_slv_axi4_ib_int_async,
  w_wpntr_gry_sdram_slv_axi4_ib_int_async,
  
// Instance: u_ib_sys_gp_apb4_ib_m, Port: sys_gp_apb4_ib_s_async

  a_data_sys_gp_apb4_ib_int_async,
  a_rpntr_gry_sys_gp_apb4_ib_int_async,
  a_rpntr_bin_sys_gp_apb4_ib_int_async,
  a_wpntr_gry_sys_gp_apb4_ib_int_async,
  d_data_sys_gp_apb4_ib_int_async,
  d_rpntr_gry_sys_gp_apb4_ib_int_async,
  d_rpntr_bin_sys_gp_apb4_ib_int_async,
  d_wpntr_gry_sys_gp_apb4_ib_int_async,
  w_data_sys_gp_apb4_ib_int_async,
  w_rpntr_gry_sys_gp_apb4_ib_int_async,
  w_rpntr_bin_sys_gp_apb4_ib_int_async,
  w_wpntr_gry_sys_gp_apb4_ib_int_async,
  
// Instance: u_ib_vgalcd_mst_axi4_ib_s, Port: vgalcd_mst_axi4_ib_m_async

  aw_data_vgalcd_mst_axi4_ib_int_async,
  aw_rpntr_gry_vgalcd_mst_axi4_ib_int_async,
  aw_rpntr_bin_vgalcd_mst_axi4_ib_int_async,
  aw_wpntr_gry_vgalcd_mst_axi4_ib_int_async,
  b_data_vgalcd_mst_axi4_ib_int_async,
  b_rpntr_gry_vgalcd_mst_axi4_ib_int_async,
  b_rpntr_bin_vgalcd_mst_axi4_ib_int_async,
  b_wpntr_gry_vgalcd_mst_axi4_ib_int_async,
  ar_data_vgalcd_mst_axi4_ib_int_async,
  ar_rpntr_gry_vgalcd_mst_axi4_ib_int_async,
  ar_rpntr_bin_vgalcd_mst_axi4_ib_int_async,
  ar_wpntr_gry_vgalcd_mst_axi4_ib_int_async,
  r_data_vgalcd_mst_axi4_ib_int_async,
  r_rpntr_gry_vgalcd_mst_axi4_ib_int_async,
  r_rpntr_bin_vgalcd_mst_axi4_ib_int_async,
  r_wpntr_gry_vgalcd_mst_axi4_ib_int_async,
  w_data_vgalcd_mst_axi4_ib_int_async,
  w_rpntr_gry_vgalcd_mst_axi4_ib_int_async,
  w_rpntr_bin_vgalcd_mst_axi4_ib_int_async,
  w_wpntr_gry_vgalcd_mst_axi4_ib_int_async,

//  Non-bus signals

  clk_peri_100mclk,
  clk_peri_100mclken,
  clk_peri_100mresetn

);



//-----------------------------------------------------------------------------
// Port Declarations
//-----------------------------------------------------------------------------


// Instance: u_amib_perip0_gp_apb4, Port: gpio_slv_apb4

output [31:0] paddr_gpio_slv_apb4;
output [31:0] pwdata_gpio_slv_apb4;
output        pwrite_gpio_slv_apb4;
output [2:0]  pprot_gpio_slv_apb4;
output [3:0]  pstrb_gpio_slv_apb4;
output        penable_gpio_slv_apb4;
output        pselx_gpio_slv_apb4;
input  [31:0] prdata_gpio_slv_apb4;
input         pslverr_gpio_slv_apb4;
input         pready_gpio_slv_apb4;

// Instance: u_amib_perip0_gp_apb4, Port: i2c_slv_apb4

output [31:0] paddr_i2c_slv_apb4;
output [31:0] pwdata_i2c_slv_apb4;
output        pwrite_i2c_slv_apb4;
output [2:0]  pprot_i2c_slv_apb4;
output [3:0]  pstrb_i2c_slv_apb4;
output        penable_i2c_slv_apb4;
output        pselx_i2c_slv_apb4;
input  [31:0] prdata_i2c_slv_apb4;
input         pslverr_i2c_slv_apb4;
input         pready_i2c_slv_apb4;

// Instance: u_amib_perip0_gp_apb4, Port: pwm0_slv_apb4

output [31:0] paddr_pwm0_slv_apb4;
output [31:0] pwdata_pwm0_slv_apb4;
output        pwrite_pwm0_slv_apb4;
output [2:0]  pprot_pwm0_slv_apb4;
output [3:0]  pstrb_pwm0_slv_apb4;
output        penable_pwm0_slv_apb4;
output        pselx_pwm0_slv_apb4;
input  [31:0] prdata_pwm0_slv_apb4;
input         pslverr_pwm0_slv_apb4;
input         pready_pwm0_slv_apb4;

// Instance: u_amib_perip0_gp_apb4, Port: pwm1_slv_apb4

output [31:0] paddr_pwm1_slv_apb4;
output [31:0] pwdata_pwm1_slv_apb4;
output        pwrite_pwm1_slv_apb4;
output [2:0]  pprot_pwm1_slv_apb4;
output [3:0]  pstrb_pwm1_slv_apb4;
output        penable_pwm1_slv_apb4;
output        pselx_pwm1_slv_apb4;
input  [31:0] prdata_pwm1_slv_apb4;
input         pslverr_pwm1_slv_apb4;
input         pready_pwm1_slv_apb4;

// Instance: u_amib_perip0_gp_apb4, Port: pwm2_slv_apb4

output [31:0] paddr_pwm2_slv_apb4;
output [31:0] pwdata_pwm2_slv_apb4;
output        pwrite_pwm2_slv_apb4;
output [2:0]  pprot_pwm2_slv_apb4;
output [3:0]  pstrb_pwm2_slv_apb4;
output        penable_pwm2_slv_apb4;
output        pselx_pwm2_slv_apb4;
input  [31:0] prdata_pwm2_slv_apb4;
input         pslverr_pwm2_slv_apb4;
input         pready_pwm2_slv_apb4;

// Instance: u_amib_perip0_gp_apb4, Port: qspi_slv_apb4

output [31:0] paddr_qspi_slv_apb4;
output [31:0] pwdata_qspi_slv_apb4;
output        pwrite_qspi_slv_apb4;
output [2:0]  pprot_qspi_slv_apb4;
output [3:0]  pstrb_qspi_slv_apb4;
output        penable_qspi_slv_apb4;
output        pselx_qspi_slv_apb4;
input  [31:0] prdata_qspi_slv_apb4;
input         pslverr_qspi_slv_apb4;
input         pready_qspi_slv_apb4;

// Instance: u_amib_perip0_gp_apb4, Port: rtc_slv_apb4

output [31:0] paddr_rtc_slv_apb4;
output [31:0] pwdata_rtc_slv_apb4;
output        pwrite_rtc_slv_apb4;
output [2:0]  pprot_rtc_slv_apb4;
output [3:0]  pstrb_rtc_slv_apb4;
output        penable_rtc_slv_apb4;
output        pselx_rtc_slv_apb4;
input  [31:0] prdata_rtc_slv_apb4;
input         pslverr_rtc_slv_apb4;
input         pready_rtc_slv_apb4;

// Instance: u_amib_perip0_gp_apb4, Port: uart_slv_apb4

output [31:0] paddr_uart_slv_apb4;
output [31:0] pwdata_uart_slv_apb4;
output        pwrite_uart_slv_apb4;
output [2:0]  pprot_uart_slv_apb4;
output [3:0]  pstrb_uart_slv_apb4;
output        penable_uart_slv_apb4;
output        pselx_uart_slv_apb4;
input  [31:0] prdata_uart_slv_apb4;
input         pslverr_uart_slv_apb4;
input         pready_uart_slv_apb4;

// Instance: u_amib_perip0_gp_apb4, Port: vgalcd_slv_apb4

output [31:0] paddr_vgalcd_slv_apb4;
output [31:0] pwdata_vgalcd_slv_apb4;
output        pwrite_vgalcd_slv_apb4;
output [2:0]  pprot_vgalcd_slv_apb4;
output [3:0]  pstrb_vgalcd_slv_apb4;
output        penable_vgalcd_slv_apb4;
output        pselx_vgalcd_slv_apb4;
input  [31:0] prdata_vgalcd_slv_apb4;
input         pslverr_vgalcd_slv_apb4;
input         pready_vgalcd_slv_apb4;

// Instance: u_amib_perip0_gp_apb4, Port: wdg_slv_apb4

output [31:0] paddr_wdg_slv_apb4;
output [31:0] pwdata_wdg_slv_apb4;
output        pwrite_wdg_slv_apb4;
output [2:0]  pprot_wdg_slv_apb4;
output [3:0]  pstrb_wdg_slv_apb4;
output        penable_wdg_slv_apb4;
output        pselx_wdg_slv_apb4;
input  [31:0] prdata_wdg_slv_apb4;
input         pslverr_wdg_slv_apb4;
input         pready_wdg_slv_apb4;

// Instance: u_amib_perip1_gp_apb4, Port: archinfo_slv_apb4

output [31:0] paddr_archinfo_slv_apb4;
output [31:0] pwdata_archinfo_slv_apb4;
output        pwrite_archinfo_slv_apb4;
output [2:0]  pprot_archinfo_slv_apb4;
output [3:0]  pstrb_archinfo_slv_apb4;
output        penable_archinfo_slv_apb4;
output        pselx_archinfo_slv_apb4;
input  [31:0] prdata_archinfo_slv_apb4;
input         pslverr_archinfo_slv_apb4;
input         pready_archinfo_slv_apb4;

// Instance: u_amib_perip1_gp_apb4, Port: crc_slv_apb4

output [31:0] paddr_crc_slv_apb4;
output [31:0] pwdata_crc_slv_apb4;
output        pwrite_crc_slv_apb4;
output [2:0]  pprot_crc_slv_apb4;
output [3:0]  pstrb_crc_slv_apb4;
output        penable_crc_slv_apb4;
output        pselx_crc_slv_apb4;
input  [31:0] prdata_crc_slv_apb4;
input         pslverr_crc_slv_apb4;
input         pready_crc_slv_apb4;

// Instance: u_amib_perip1_gp_apb4, Port: ps2_slv_apb4

output [31:0] paddr_ps2_slv_apb4;
output [31:0] pwdata_ps2_slv_apb4;
output        pwrite_ps2_slv_apb4;
output [2:0]  pprot_ps2_slv_apb4;
output [3:0]  pstrb_ps2_slv_apb4;
output        penable_ps2_slv_apb4;
output        pselx_ps2_slv_apb4;
input  [31:0] prdata_ps2_slv_apb4;
input         pslverr_ps2_slv_apb4;
input         pready_ps2_slv_apb4;

// Instance: u_amib_perip1_gp_apb4, Port: psram_slv_apb4

output [31:0] paddr_psram_slv_apb4;
output [31:0] pwdata_psram_slv_apb4;
output        pwrite_psram_slv_apb4;
output [2:0]  pprot_psram_slv_apb4;
output [3:0]  pstrb_psram_slv_apb4;
output        penable_psram_slv_apb4;
output        pselx_psram_slv_apb4;
input  [31:0] prdata_psram_slv_apb4;
input         pslverr_psram_slv_apb4;
input         pready_psram_slv_apb4;

// Instance: u_amib_perip1_gp_apb4, Port: rng_slv_apb4

output [31:0] paddr_rng_slv_apb4;
output [31:0] pwdata_rng_slv_apb4;
output        pwrite_rng_slv_apb4;
output [2:0]  pprot_rng_slv_apb4;
output [3:0]  pstrb_rng_slv_apb4;
output        penable_rng_slv_apb4;
output        pselx_rng_slv_apb4;
input  [31:0] prdata_rng_slv_apb4;
input         pslverr_rng_slv_apb4;
input         pready_rng_slv_apb4;

// Instance: u_amib_perip1_gp_apb4, Port: spi0_slv_apb4

output [31:0] paddr_spi0_slv_apb4;
output [31:0] pwdata_spi0_slv_apb4;
output        pwrite_spi0_slv_apb4;
output [2:0]  pprot_spi0_slv_apb4;
output [3:0]  pstrb_spi0_slv_apb4;
output        penable_spi0_slv_apb4;
output        pselx_spi0_slv_apb4;
input  [31:0] prdata_spi0_slv_apb4;
input         pslverr_spi0_slv_apb4;
input         pready_spi0_slv_apb4;

// Instance: u_amib_perip1_gp_apb4, Port: spi1_slv_apb4

output [31:0] paddr_spi1_slv_apb4;
output [31:0] pwdata_spi1_slv_apb4;
output        pwrite_spi1_slv_apb4;
output [2:0]  pprot_spi1_slv_apb4;
output [3:0]  pstrb_spi1_slv_apb4;
output        penable_spi1_slv_apb4;
output        pselx_spi1_slv_apb4;
input  [31:0] prdata_spi1_slv_apb4;
input         pslverr_spi1_slv_apb4;
input         pready_spi1_slv_apb4;

// Instance: u_amib_perip1_gp_apb4, Port: tim0_slv_apb4

output [31:0] paddr_tim0_slv_apb4;
output [31:0] pwdata_tim0_slv_apb4;
output        pwrite_tim0_slv_apb4;
output [2:0]  pprot_tim0_slv_apb4;
output [3:0]  pstrb_tim0_slv_apb4;
output        penable_tim0_slv_apb4;
output        pselx_tim0_slv_apb4;
input  [31:0] prdata_tim0_slv_apb4;
input         pslverr_tim0_slv_apb4;
input         pready_tim0_slv_apb4;

// Instance: u_amib_perip1_gp_apb4, Port: tim1_slv_apb4

output [31:0] paddr_tim1_slv_apb4;
output [31:0] pwdata_tim1_slv_apb4;
output        pwrite_tim1_slv_apb4;
output [2:0]  pprot_tim1_slv_apb4;
output [3:0]  pstrb_tim1_slv_apb4;
output        penable_tim1_slv_apb4;
output        pselx_tim1_slv_apb4;
input  [31:0] prdata_tim1_slv_apb4;
input         pslverr_tim1_slv_apb4;
input         pready_tim1_slv_apb4;

// Instance: u_amib_perip1_gp_apb4, Port: tim2_slv_apb4

output [31:0] paddr_tim2_slv_apb4;
output [31:0] pwdata_tim2_slv_apb4;
output        pwrite_tim2_slv_apb4;
output [2:0]  pprot_tim2_slv_apb4;
output [3:0]  pstrb_tim2_slv_apb4;
output        penable_tim2_slv_apb4;
output        pselx_tim2_slv_apb4;
input  [31:0] prdata_tim2_slv_apb4;
input         pslverr_tim2_slv_apb4;
input         pready_tim2_slv_apb4;

// Instance: u_amib_perip1_gp_apb4, Port: tim3_slv_apb4

output [31:0] paddr_tim3_slv_apb4;
output [31:0] pwdata_tim3_slv_apb4;
output        pwrite_tim3_slv_apb4;
output [2:0]  pprot_tim3_slv_apb4;
output [3:0]  pstrb_tim3_slv_apb4;
output        penable_tim3_slv_apb4;
output        pselx_tim3_slv_apb4;
input  [31:0] prdata_tim3_slv_apb4;
input         pslverr_tim3_slv_apb4;
input         pready_tim3_slv_apb4;

// Instance: u_amib_psram_slv_axi4, Port: psram_slv_axi4_m

output [3:0]  awid_psram_slv_axi4;
output [31:0] awaddr_psram_slv_axi4;
output [7:0]  awlen_psram_slv_axi4;
output [2:0]  awsize_psram_slv_axi4;
output [1:0]  awburst_psram_slv_axi4;
output        awlock_psram_slv_axi4;
output [3:0]  awcache_psram_slv_axi4;
output [2:0]  awprot_psram_slv_axi4;
output        awvalid_psram_slv_axi4;
input         awready_psram_slv_axi4;
output [63:0] wdata_psram_slv_axi4;
output [7:0]  wstrb_psram_slv_axi4;
output        wlast_psram_slv_axi4;
output        wvalid_psram_slv_axi4;
input         wready_psram_slv_axi4;
input  [3:0]  bid_psram_slv_axi4;
input  [1:0]  bresp_psram_slv_axi4;
input         bvalid_psram_slv_axi4;
output        bready_psram_slv_axi4;
output [3:0]  arid_psram_slv_axi4;
output [31:0] araddr_psram_slv_axi4;
output [7:0]  arlen_psram_slv_axi4;
output [2:0]  arsize_psram_slv_axi4;
output [1:0]  arburst_psram_slv_axi4;
output        arlock_psram_slv_axi4;
output [3:0]  arcache_psram_slv_axi4;
output [2:0]  arprot_psram_slv_axi4;
output        arvalid_psram_slv_axi4;
input         arready_psram_slv_axi4;
input  [3:0]  rid_psram_slv_axi4;
input  [63:0] rdata_psram_slv_axi4;
input  [1:0]  rresp_psram_slv_axi4;
input         rlast_psram_slv_axi4;
input         rvalid_psram_slv_axi4;
output        rready_psram_slv_axi4;

// Instance: u_amib_sdram_slv_axi4, Port: sdram_slv_axi4_m

output [3:0]  awid_sdram_slv_axi4;
output [31:0] awaddr_sdram_slv_axi4;
output [7:0]  awlen_sdram_slv_axi4;
output [2:0]  awsize_sdram_slv_axi4;
output [1:0]  awburst_sdram_slv_axi4;
output        awlock_sdram_slv_axi4;
output [3:0]  awcache_sdram_slv_axi4;
output [2:0]  awprot_sdram_slv_axi4;
output        awvalid_sdram_slv_axi4;
input         awready_sdram_slv_axi4;
output [31:0] wdata_sdram_slv_axi4;
output [3:0]  wstrb_sdram_slv_axi4;
output        wlast_sdram_slv_axi4;
output        wvalid_sdram_slv_axi4;
input         wready_sdram_slv_axi4;
input  [3:0]  bid_sdram_slv_axi4;
input  [1:0]  bresp_sdram_slv_axi4;
input         bvalid_sdram_slv_axi4;
output        bready_sdram_slv_axi4;
output [3:0]  arid_sdram_slv_axi4;
output [31:0] araddr_sdram_slv_axi4;
output [7:0]  arlen_sdram_slv_axi4;
output [2:0]  arsize_sdram_slv_axi4;
output [1:0]  arburst_sdram_slv_axi4;
output        arlock_sdram_slv_axi4;
output [3:0]  arcache_sdram_slv_axi4;
output [2:0]  arprot_sdram_slv_axi4;
output        arvalid_sdram_slv_axi4;
input         arready_sdram_slv_axi4;
input  [3:0]  rid_sdram_slv_axi4;
input  [31:0] rdata_sdram_slv_axi4;
input  [1:0]  rresp_sdram_slv_axi4;
input         rlast_sdram_slv_axi4;
input         rvalid_sdram_slv_axi4;
output        rready_sdram_slv_axi4;

// Instance: u_amib_sys_gp_apb4, Port: clint_slv_apb4

output [31:0] paddr_clint_slv_apb4;
output [31:0] pwdata_clint_slv_apb4;
output        pwrite_clint_slv_apb4;
output [2:0]  pprot_clint_slv_apb4;
output [3:0]  pstrb_clint_slv_apb4;
output        penable_clint_slv_apb4;
output        pselx_clint_slv_apb4;
input  [31:0] prdata_clint_slv_apb4;
input         pslverr_clint_slv_apb4;
input         pready_clint_slv_apb4;

// Instance: u_amib_sys_gp_apb4, Port: plic_slv_apb4

output [31:0] paddr_plic_slv_apb4;
output [31:0] pwdata_plic_slv_apb4;
output        pwrite_plic_slv_apb4;
output [2:0]  pprot_plic_slv_apb4;
output [3:0]  pstrb_plic_slv_apb4;
output        penable_plic_slv_apb4;
output        pselx_plic_slv_apb4;
input  [31:0] prdata_plic_slv_apb4;
input         pslverr_plic_slv_apb4;
input         pready_plic_slv_apb4;

// Instance: u_amib_sys_gp_apb4, Port: rcu_slv_apb4

output [31:0] paddr_rcu_slv_apb4;
output [31:0] pwdata_rcu_slv_apb4;
output        pwrite_rcu_slv_apb4;
output [2:0]  pprot_rcu_slv_apb4;
output [3:0]  pstrb_rcu_slv_apb4;
output        penable_rcu_slv_apb4;
output        pselx_rcu_slv_apb4;
input  [31:0] prdata_rcu_slv_apb4;
input         pslverr_rcu_slv_apb4;
input         pready_rcu_slv_apb4;

// Instance: u_asib_vgalcd_mst_axi4, Port: vgalcd_mst_axi4_s

input  [2:0]  awid_vgalcd_mst_axi4;
input  [31:0] awaddr_vgalcd_mst_axi4;
input  [7:0]  awlen_vgalcd_mst_axi4;
input  [2:0]  awsize_vgalcd_mst_axi4;
input  [1:0]  awburst_vgalcd_mst_axi4;
input         awlock_vgalcd_mst_axi4;
input  [3:0]  awcache_vgalcd_mst_axi4;
input  [2:0]  awprot_vgalcd_mst_axi4;
input         awvalid_vgalcd_mst_axi4;
output        awready_vgalcd_mst_axi4;
input  [63:0] wdata_vgalcd_mst_axi4;
input  [7:0]  wstrb_vgalcd_mst_axi4;
input         wlast_vgalcd_mst_axi4;
input         wvalid_vgalcd_mst_axi4;
output        wready_vgalcd_mst_axi4;
output [2:0]  bid_vgalcd_mst_axi4;
output [1:0]  bresp_vgalcd_mst_axi4;
output        bvalid_vgalcd_mst_axi4;
input         bready_vgalcd_mst_axi4;
input  [2:0]  arid_vgalcd_mst_axi4;
input  [31:0] araddr_vgalcd_mst_axi4;
input  [7:0]  arlen_vgalcd_mst_axi4;
input  [2:0]  arsize_vgalcd_mst_axi4;
input  [1:0]  arburst_vgalcd_mst_axi4;
input         arlock_vgalcd_mst_axi4;
input  [3:0]  arcache_vgalcd_mst_axi4;
input  [2:0]  arprot_vgalcd_mst_axi4;
input         arvalid_vgalcd_mst_axi4;
output        arready_vgalcd_mst_axi4;
output [2:0]  rid_vgalcd_mst_axi4;
output [63:0] rdata_vgalcd_mst_axi4;
output [1:0]  rresp_vgalcd_mst_axi4;
output        rlast_vgalcd_mst_axi4;
output        rvalid_vgalcd_mst_axi4;
input         rready_vgalcd_mst_axi4;

// Instance: u_ib_perip0_gp_apb4_ib_m, Port: perip0_gp_apb4_ib_s_async

input  [61:0] a_data_perip0_gp_apb4_ib_int_async;
output [1:0]  a_rpntr_gry_perip0_gp_apb4_ib_int_async;
output        a_rpntr_bin_perip0_gp_apb4_ib_int_async;
input  [1:0]  a_wpntr_gry_perip0_gp_apb4_ib_int_async;
output [39:0] d_data_perip0_gp_apb4_ib_int_async;
input  [1:0]  d_rpntr_gry_perip0_gp_apb4_ib_int_async;
input         d_rpntr_bin_perip0_gp_apb4_ib_int_async;
output [1:0]  d_wpntr_gry_perip0_gp_apb4_ib_int_async;
input  [36:0] w_data_perip0_gp_apb4_ib_int_async;
output [1:0]  w_rpntr_gry_perip0_gp_apb4_ib_int_async;
output        w_rpntr_bin_perip0_gp_apb4_ib_int_async;
input  [1:0]  w_wpntr_gry_perip0_gp_apb4_ib_int_async;

// Instance: u_ib_perip1_gp_apb4_ib_m, Port: perip1_gp_apb4_ib_s_async

input  [61:0] a_data_perip1_gp_apb4_ib_int_async;
output [1:0]  a_rpntr_gry_perip1_gp_apb4_ib_int_async;
output        a_rpntr_bin_perip1_gp_apb4_ib_int_async;
input  [1:0]  a_wpntr_gry_perip1_gp_apb4_ib_int_async;
output [39:0] d_data_perip1_gp_apb4_ib_int_async;
input  [1:0]  d_rpntr_gry_perip1_gp_apb4_ib_int_async;
input         d_rpntr_bin_perip1_gp_apb4_ib_int_async;
output [1:0]  d_wpntr_gry_perip1_gp_apb4_ib_int_async;
input  [36:0] w_data_perip1_gp_apb4_ib_int_async;
output [1:0]  w_rpntr_gry_perip1_gp_apb4_ib_int_async;
output        w_rpntr_bin_perip1_gp_apb4_ib_int_async;
input  [1:0]  w_wpntr_gry_perip1_gp_apb4_ib_int_async;

// Instance: u_ib_psram_slv_axi4_ib_m, Port: psram_slv_axi4_ib_s_async

input  [60:0] aw_data_psram_slv_axi4_ib_int_async;
output [1:0]  aw_rpntr_gry_psram_slv_axi4_ib_int_async;
output        aw_rpntr_bin_psram_slv_axi4_ib_int_async;
input  [1:0]  aw_wpntr_gry_psram_slv_axi4_ib_int_async;
output [5:0]  b_data_psram_slv_axi4_ib_int_async;
input  [1:0]  b_rpntr_gry_psram_slv_axi4_ib_int_async;
input         b_rpntr_bin_psram_slv_axi4_ib_int_async;
output [1:0]  b_wpntr_gry_psram_slv_axi4_ib_int_async;
input  [60:0] ar_data_psram_slv_axi4_ib_int_async;
output [1:0]  ar_rpntr_gry_psram_slv_axi4_ib_int_async;
output        ar_rpntr_bin_psram_slv_axi4_ib_int_async;
input  [1:0]  ar_wpntr_gry_psram_slv_axi4_ib_int_async;
output [70:0] r_data_psram_slv_axi4_ib_int_async;
input  [1:0]  r_rpntr_gry_psram_slv_axi4_ib_int_async;
input         r_rpntr_bin_psram_slv_axi4_ib_int_async;
output [1:0]  r_wpntr_gry_psram_slv_axi4_ib_int_async;
input  [72:0] w_data_psram_slv_axi4_ib_int_async;
output [1:0]  w_rpntr_gry_psram_slv_axi4_ib_int_async;
output        w_rpntr_bin_psram_slv_axi4_ib_int_async;
input  [1:0]  w_wpntr_gry_psram_slv_axi4_ib_int_async;

// Instance: u_ib_sdram_slv_axi4_ib_m, Port: sdram_slv_axi4_ib_s_async

input  [60:0] aw_data_sdram_slv_axi4_ib_int_async;
output [1:0]  aw_rpntr_gry_sdram_slv_axi4_ib_int_async;
output        aw_rpntr_bin_sdram_slv_axi4_ib_int_async;
input  [1:0]  aw_wpntr_gry_sdram_slv_axi4_ib_int_async;
output [5:0]  b_data_sdram_slv_axi4_ib_int_async;
input  [1:0]  b_rpntr_gry_sdram_slv_axi4_ib_int_async;
input         b_rpntr_bin_sdram_slv_axi4_ib_int_async;
output [1:0]  b_wpntr_gry_sdram_slv_axi4_ib_int_async;
input  [60:0] ar_data_sdram_slv_axi4_ib_int_async;
output [1:0]  ar_rpntr_gry_sdram_slv_axi4_ib_int_async;
output        ar_rpntr_bin_sdram_slv_axi4_ib_int_async;
input  [1:0]  ar_wpntr_gry_sdram_slv_axi4_ib_int_async;
output [38:0] r_data_sdram_slv_axi4_ib_int_async;
input  [1:0]  r_rpntr_gry_sdram_slv_axi4_ib_int_async;
input         r_rpntr_bin_sdram_slv_axi4_ib_int_async;
output [1:0]  r_wpntr_gry_sdram_slv_axi4_ib_int_async;
input  [36:0] w_data_sdram_slv_axi4_ib_int_async;
output [1:0]  w_rpntr_gry_sdram_slv_axi4_ib_int_async;
output        w_rpntr_bin_sdram_slv_axi4_ib_int_async;
input  [1:0]  w_wpntr_gry_sdram_slv_axi4_ib_int_async;

// Instance: u_ib_sys_gp_apb4_ib_m, Port: sys_gp_apb4_ib_s_async

input  [61:0] a_data_sys_gp_apb4_ib_int_async;
output [1:0]  a_rpntr_gry_sys_gp_apb4_ib_int_async;
output        a_rpntr_bin_sys_gp_apb4_ib_int_async;
input  [1:0]  a_wpntr_gry_sys_gp_apb4_ib_int_async;
output [39:0] d_data_sys_gp_apb4_ib_int_async;
input  [1:0]  d_rpntr_gry_sys_gp_apb4_ib_int_async;
input         d_rpntr_bin_sys_gp_apb4_ib_int_async;
output [1:0]  d_wpntr_gry_sys_gp_apb4_ib_int_async;
input  [36:0] w_data_sys_gp_apb4_ib_int_async;
output [1:0]  w_rpntr_gry_sys_gp_apb4_ib_int_async;
output        w_rpntr_bin_sys_gp_apb4_ib_int_async;
input  [1:0]  w_wpntr_gry_sys_gp_apb4_ib_int_async;

// Instance: u_ib_vgalcd_mst_axi4_ib_s, Port: vgalcd_mst_axi4_ib_m_async

output [64:0] aw_data_vgalcd_mst_axi4_ib_int_async;
input  [1:0]  aw_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
input         aw_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
output [1:0]  aw_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
input  [4:0]  b_data_vgalcd_mst_axi4_ib_int_async;
output [1:0]  b_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
output        b_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
input  [1:0]  b_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
output [75:0] ar_data_vgalcd_mst_axi4_ib_int_async;
input  [1:0]  ar_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
input         ar_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
output [1:0]  ar_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
input  [71:0] r_data_vgalcd_mst_axi4_ib_int_async;
output [1:0]  r_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
output        r_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
input  [1:0]  r_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
output [72:0] w_data_vgalcd_mst_axi4_ib_int_async;
input  [1:0]  w_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
input         w_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
output [1:0]  w_wpntr_gry_vgalcd_mst_axi4_ib_int_async;

//  Non-bus signals

input         clk_peri_100mclk;
input         clk_peri_100mclken;
input         clk_peri_100mresetn;



//-----------------------------------------------------------------------------
// Internal Wire Declarations
//-----------------------------------------------------------------------------

wire           a_rpntr_bin_perip0_gp_apb4_ib_int_async;
wire           a_rpntr_bin_perip1_gp_apb4_ib_int_async;
wire           a_rpntr_bin_sys_gp_apb4_ib_int_async;
wire   [1:0]   a_rpntr_gry_perip0_gp_apb4_ib_int_async;
wire   [1:0]   a_rpntr_gry_perip1_gp_apb4_ib_int_async;
wire   [1:0]   a_rpntr_gry_sys_gp_apb4_ib_int_async;
wire   [75:0]  ar_data_vgalcd_mst_axi4_ib_int_async;
wire           ar_rpntr_bin_psram_slv_axi4_ib_int_async;
wire           ar_rpntr_bin_sdram_slv_axi4_ib_int_async;
wire   [1:0]   ar_rpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   ar_rpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [1:0]   ar_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [31:0]  araddr_psram_slv_axi4;
wire   [31:0]  araddr_sdram_slv_axi4;
wire   [1:0]   arburst_psram_slv_axi4;
wire   [1:0]   arburst_sdram_slv_axi4;
wire   [3:0]   arcache_psram_slv_axi4;
wire   [3:0]   arcache_sdram_slv_axi4;
wire   [3:0]   arid_psram_slv_axi4;
wire   [3:0]   arid_sdram_slv_axi4;
wire   [7:0]   arlen_psram_slv_axi4;
wire   [7:0]   arlen_sdram_slv_axi4;
wire           arlock_psram_slv_axi4;
wire           arlock_sdram_slv_axi4;
wire   [2:0]   arprot_psram_slv_axi4;
wire   [2:0]   arprot_sdram_slv_axi4;
wire           arready_vgalcd_mst_axi4;
wire   [2:0]   arsize_psram_slv_axi4;
wire   [2:0]   arsize_sdram_slv_axi4;
wire           arvalid_psram_slv_axi4;
wire           arvalid_sdram_slv_axi4;
wire   [64:0]  aw_data_vgalcd_mst_axi4_ib_int_async;
wire           aw_rpntr_bin_psram_slv_axi4_ib_int_async;
wire           aw_rpntr_bin_sdram_slv_axi4_ib_int_async;
wire   [1:0]   aw_rpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   aw_rpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [1:0]   aw_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [31:0]  awaddr_psram_slv_axi4;
wire   [31:0]  awaddr_sdram_slv_axi4;
wire   [1:0]   awburst_psram_slv_axi4;
wire   [1:0]   awburst_sdram_slv_axi4;
wire   [3:0]   awcache_psram_slv_axi4;
wire   [3:0]   awcache_sdram_slv_axi4;
wire   [3:0]   awid_psram_slv_axi4;
wire   [3:0]   awid_sdram_slv_axi4;
wire   [7:0]   awlen_psram_slv_axi4;
wire   [7:0]   awlen_sdram_slv_axi4;
wire           awlock_psram_slv_axi4;
wire           awlock_sdram_slv_axi4;
wire   [2:0]   awprot_psram_slv_axi4;
wire   [2:0]   awprot_sdram_slv_axi4;
wire           awready_vgalcd_mst_axi4;
wire   [2:0]   awsize_psram_slv_axi4;
wire   [2:0]   awsize_sdram_slv_axi4;
wire           awvalid_psram_slv_axi4;
wire           awvalid_sdram_slv_axi4;
wire   [5:0]   b_data_psram_slv_axi4_ib_int_async;
wire   [5:0]   b_data_sdram_slv_axi4_ib_int_async;
wire           b_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   b_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   b_wpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   b_wpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [2:0]   bid_vgalcd_mst_axi4;
wire           bready_psram_slv_axi4;
wire           bready_sdram_slv_axi4;
wire   [1:0]   bresp_vgalcd_mst_axi4;
wire           bvalid_vgalcd_mst_axi4;
wire   [39:0]  d_data_perip0_gp_apb4_ib_int_async;
wire   [39:0]  d_data_perip1_gp_apb4_ib_int_async;
wire   [39:0]  d_data_sys_gp_apb4_ib_int_async;
wire   [1:0]   d_wpntr_gry_perip0_gp_apb4_ib_int_async;
wire   [1:0]   d_wpntr_gry_perip1_gp_apb4_ib_int_async;
wire   [1:0]   d_wpntr_gry_sys_gp_apb4_ib_int_async;
wire   [31:0]  paddr_archinfo_slv_apb4;
wire   [31:0]  paddr_clint_slv_apb4;
wire   [31:0]  paddr_crc_slv_apb4;
wire   [31:0]  paddr_gpio_slv_apb4;
wire   [31:0]  paddr_i2c_slv_apb4;
wire   [31:0]  paddr_plic_slv_apb4;
wire   [31:0]  paddr_ps2_slv_apb4;
wire   [31:0]  paddr_psram_slv_apb4;
wire   [31:0]  paddr_pwm0_slv_apb4;
wire   [31:0]  paddr_pwm1_slv_apb4;
wire   [31:0]  paddr_pwm2_slv_apb4;
wire   [31:0]  paddr_qspi_slv_apb4;
wire   [31:0]  paddr_rcu_slv_apb4;
wire   [31:0]  paddr_rng_slv_apb4;
wire   [31:0]  paddr_rtc_slv_apb4;
wire   [31:0]  paddr_spi0_slv_apb4;
wire   [31:0]  paddr_spi1_slv_apb4;
wire   [31:0]  paddr_tim0_slv_apb4;
wire   [31:0]  paddr_tim1_slv_apb4;
wire   [31:0]  paddr_tim2_slv_apb4;
wire   [31:0]  paddr_tim3_slv_apb4;
wire   [31:0]  paddr_uart_slv_apb4;
wire   [31:0]  paddr_vgalcd_slv_apb4;
wire   [31:0]  paddr_wdg_slv_apb4;
wire           penable_archinfo_slv_apb4;
wire           penable_clint_slv_apb4;
wire           penable_crc_slv_apb4;
wire           penable_gpio_slv_apb4;
wire           penable_i2c_slv_apb4;
wire           penable_plic_slv_apb4;
wire           penable_ps2_slv_apb4;
wire           penable_psram_slv_apb4;
wire           penable_pwm0_slv_apb4;
wire           penable_pwm1_slv_apb4;
wire           penable_pwm2_slv_apb4;
wire           penable_qspi_slv_apb4;
wire           penable_rcu_slv_apb4;
wire           penable_rng_slv_apb4;
wire           penable_rtc_slv_apb4;
wire           penable_spi0_slv_apb4;
wire           penable_spi1_slv_apb4;
wire           penable_tim0_slv_apb4;
wire           penable_tim1_slv_apb4;
wire           penable_tim2_slv_apb4;
wire           penable_tim3_slv_apb4;
wire           penable_uart_slv_apb4;
wire           penable_vgalcd_slv_apb4;
wire           penable_wdg_slv_apb4;
wire   [2:0]   pprot_archinfo_slv_apb4;
wire   [2:0]   pprot_clint_slv_apb4;
wire   [2:0]   pprot_crc_slv_apb4;
wire   [2:0]   pprot_gpio_slv_apb4;
wire   [2:0]   pprot_i2c_slv_apb4;
wire   [2:0]   pprot_plic_slv_apb4;
wire   [2:0]   pprot_ps2_slv_apb4;
wire   [2:0]   pprot_psram_slv_apb4;
wire   [2:0]   pprot_pwm0_slv_apb4;
wire   [2:0]   pprot_pwm1_slv_apb4;
wire   [2:0]   pprot_pwm2_slv_apb4;
wire   [2:0]   pprot_qspi_slv_apb4;
wire   [2:0]   pprot_rcu_slv_apb4;
wire   [2:0]   pprot_rng_slv_apb4;
wire   [2:0]   pprot_rtc_slv_apb4;
wire   [2:0]   pprot_spi0_slv_apb4;
wire   [2:0]   pprot_spi1_slv_apb4;
wire   [2:0]   pprot_tim0_slv_apb4;
wire   [2:0]   pprot_tim1_slv_apb4;
wire   [2:0]   pprot_tim2_slv_apb4;
wire   [2:0]   pprot_tim3_slv_apb4;
wire   [2:0]   pprot_uart_slv_apb4;
wire   [2:0]   pprot_vgalcd_slv_apb4;
wire   [2:0]   pprot_wdg_slv_apb4;
wire           pselx_archinfo_slv_apb4;
wire           pselx_clint_slv_apb4;
wire           pselx_crc_slv_apb4;
wire           pselx_gpio_slv_apb4;
wire           pselx_i2c_slv_apb4;
wire           pselx_plic_slv_apb4;
wire           pselx_ps2_slv_apb4;
wire           pselx_psram_slv_apb4;
wire           pselx_pwm0_slv_apb4;
wire           pselx_pwm1_slv_apb4;
wire           pselx_pwm2_slv_apb4;
wire           pselx_qspi_slv_apb4;
wire           pselx_rcu_slv_apb4;
wire           pselx_rng_slv_apb4;
wire           pselx_rtc_slv_apb4;
wire           pselx_spi0_slv_apb4;
wire           pselx_spi1_slv_apb4;
wire           pselx_tim0_slv_apb4;
wire           pselx_tim1_slv_apb4;
wire           pselx_tim2_slv_apb4;
wire           pselx_tim3_slv_apb4;
wire           pselx_uart_slv_apb4;
wire           pselx_vgalcd_slv_apb4;
wire           pselx_wdg_slv_apb4;
wire   [3:0]   pstrb_archinfo_slv_apb4;
wire   [3:0]   pstrb_clint_slv_apb4;
wire   [3:0]   pstrb_crc_slv_apb4;
wire   [3:0]   pstrb_gpio_slv_apb4;
wire   [3:0]   pstrb_i2c_slv_apb4;
wire   [3:0]   pstrb_plic_slv_apb4;
wire   [3:0]   pstrb_ps2_slv_apb4;
wire   [3:0]   pstrb_psram_slv_apb4;
wire   [3:0]   pstrb_pwm0_slv_apb4;
wire   [3:0]   pstrb_pwm1_slv_apb4;
wire   [3:0]   pstrb_pwm2_slv_apb4;
wire   [3:0]   pstrb_qspi_slv_apb4;
wire   [3:0]   pstrb_rcu_slv_apb4;
wire   [3:0]   pstrb_rng_slv_apb4;
wire   [3:0]   pstrb_rtc_slv_apb4;
wire   [3:0]   pstrb_spi0_slv_apb4;
wire   [3:0]   pstrb_spi1_slv_apb4;
wire   [3:0]   pstrb_tim0_slv_apb4;
wire   [3:0]   pstrb_tim1_slv_apb4;
wire   [3:0]   pstrb_tim2_slv_apb4;
wire   [3:0]   pstrb_tim3_slv_apb4;
wire   [3:0]   pstrb_uart_slv_apb4;
wire   [3:0]   pstrb_vgalcd_slv_apb4;
wire   [3:0]   pstrb_wdg_slv_apb4;
wire   [31:0]  pwdata_archinfo_slv_apb4;
wire   [31:0]  pwdata_clint_slv_apb4;
wire   [31:0]  pwdata_crc_slv_apb4;
wire   [31:0]  pwdata_gpio_slv_apb4;
wire   [31:0]  pwdata_i2c_slv_apb4;
wire   [31:0]  pwdata_plic_slv_apb4;
wire   [31:0]  pwdata_ps2_slv_apb4;
wire   [31:0]  pwdata_psram_slv_apb4;
wire   [31:0]  pwdata_pwm0_slv_apb4;
wire   [31:0]  pwdata_pwm1_slv_apb4;
wire   [31:0]  pwdata_pwm2_slv_apb4;
wire   [31:0]  pwdata_qspi_slv_apb4;
wire   [31:0]  pwdata_rcu_slv_apb4;
wire   [31:0]  pwdata_rng_slv_apb4;
wire   [31:0]  pwdata_rtc_slv_apb4;
wire   [31:0]  pwdata_spi0_slv_apb4;
wire   [31:0]  pwdata_spi1_slv_apb4;
wire   [31:0]  pwdata_tim0_slv_apb4;
wire   [31:0]  pwdata_tim1_slv_apb4;
wire   [31:0]  pwdata_tim2_slv_apb4;
wire   [31:0]  pwdata_tim3_slv_apb4;
wire   [31:0]  pwdata_uart_slv_apb4;
wire   [31:0]  pwdata_vgalcd_slv_apb4;
wire   [31:0]  pwdata_wdg_slv_apb4;
wire           pwrite_archinfo_slv_apb4;
wire           pwrite_clint_slv_apb4;
wire           pwrite_crc_slv_apb4;
wire           pwrite_gpio_slv_apb4;
wire           pwrite_i2c_slv_apb4;
wire           pwrite_plic_slv_apb4;
wire           pwrite_ps2_slv_apb4;
wire           pwrite_psram_slv_apb4;
wire           pwrite_pwm0_slv_apb4;
wire           pwrite_pwm1_slv_apb4;
wire           pwrite_pwm2_slv_apb4;
wire           pwrite_qspi_slv_apb4;
wire           pwrite_rcu_slv_apb4;
wire           pwrite_rng_slv_apb4;
wire           pwrite_rtc_slv_apb4;
wire           pwrite_spi0_slv_apb4;
wire           pwrite_spi1_slv_apb4;
wire           pwrite_tim0_slv_apb4;
wire           pwrite_tim1_slv_apb4;
wire           pwrite_tim2_slv_apb4;
wire           pwrite_tim3_slv_apb4;
wire           pwrite_uart_slv_apb4;
wire           pwrite_vgalcd_slv_apb4;
wire           pwrite_wdg_slv_apb4;
wire   [70:0]  r_data_psram_slv_axi4_ib_int_async;
wire   [38:0]  r_data_sdram_slv_axi4_ib_int_async;
wire           r_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   r_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   r_wpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   r_wpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [63:0]  rdata_vgalcd_mst_axi4;
wire   [2:0]   rid_vgalcd_mst_axi4;
wire           rlast_vgalcd_mst_axi4;
wire           rready_psram_slv_axi4;
wire           rready_sdram_slv_axi4;
wire   [1:0]   rresp_vgalcd_mst_axi4;
wire           rvalid_vgalcd_mst_axi4;
wire   [72:0]  w_data_vgalcd_mst_axi4_ib_int_async;
wire           w_rpntr_bin_perip0_gp_apb4_ib_int_async;
wire           w_rpntr_bin_perip1_gp_apb4_ib_int_async;
wire           w_rpntr_bin_psram_slv_axi4_ib_int_async;
wire           w_rpntr_bin_sdram_slv_axi4_ib_int_async;
wire           w_rpntr_bin_sys_gp_apb4_ib_int_async;
wire   [1:0]   w_rpntr_gry_perip0_gp_apb4_ib_int_async;
wire   [1:0]   w_rpntr_gry_perip1_gp_apb4_ib_int_async;
wire   [1:0]   w_rpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   w_rpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [1:0]   w_rpntr_gry_sys_gp_apb4_ib_int_async;
wire   [1:0]   w_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [63:0]  wdata_psram_slv_axi4;
wire   [31:0]  wdata_sdram_slv_axi4;
wire           wlast_psram_slv_axi4;
wire           wlast_sdram_slv_axi4;
wire           wready_vgalcd_mst_axi4;
wire   [7:0]   wstrb_psram_slv_axi4;
wire   [3:0]   wstrb_sdram_slv_axi4;
wire           wvalid_psram_slv_axi4;
wire           wvalid_sdram_slv_axi4;
wire           aready_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire           dbnr_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire   [31:0]  ddata_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire   [3:0]   did_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire           dlast_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire   [1:0]   dresp_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire           dvalid_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire           wready_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire           aready_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire           dbnr_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire   [31:0]  ddata_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire   [3:0]   did_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire           dlast_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire   [1:0]   dresp_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire           dvalid_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire           wready_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire           arready_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire           awready_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [3:0]   bid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [1:0]   bresp_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire           bvalid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [63:0]  rdata_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [3:0]   rid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire           rlast_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [1:0]   rresp_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire           rvalid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire           wready_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire           arready_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire           awready_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [3:0]   bid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [1:0]   bresp_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire           bvalid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [31:0]  rdata_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [3:0]   rid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire           rlast_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [1:0]   rresp_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire           rvalid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire           wready_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire           aready_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire           dbnr_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire   [31:0]  ddata_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire   [3:0]   did_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire           dlast_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire   [1:0]   dresp_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire           dvalid_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire           wready_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire   [31:0]  araddr_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [1:0]   arburst_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [3:0]   arcache_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [2:0]   arid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [7:0]   arlen_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire           arlock_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [2:0]   arprot_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [3:0]   arregion_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [2:0]   arsize_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [3:0]   arvalid_vect_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire           arvalid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [31:0]  awaddr_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [1:0]   awburst_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [3:0]   awcache_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [2:0]   awid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [7:0]   awlen_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire           awlock_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [2:0]   awprot_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [3:0]   awregion_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [2:0]   awsize_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [3:0]   awvalid_vect_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire           awvalid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire           bready_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire           rready_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [63:0]  wdata_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire           wlast_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [7:0]   wstrb_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire           wvalid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [31:0]  aaddr_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire   [1:0]   aburst_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire   [3:0]   acache_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire   [3:0]   aid_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire   [7:0]   alen_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire           alock_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire   [2:0]   aprot_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire   [3:0]   aregion_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire   [2:0]   asize_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire           avalid_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire           awrite_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire           dready_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire   [31:0]  wdata_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire           wlast_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire   [3:0]   wstrb_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire           wvalid_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s;
wire   [31:0]  aaddr_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire   [1:0]   aburst_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire   [3:0]   acache_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire   [3:0]   aid_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire   [7:0]   alen_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire           alock_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire   [2:0]   aprot_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire   [3:0]   aregion_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire   [2:0]   asize_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire           avalid_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire           awrite_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire           dready_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire   [31:0]  wdata_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire           wlast_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire   [3:0]   wstrb_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire           wvalid_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s;
wire   [31:0]  araddr_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [1:0]   arburst_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [3:0]   arcache_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [3:0]   arid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [7:0]   arlen_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire           arlock_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [2:0]   arprot_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [2:0]   arsize_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire           arvalid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [31:0]  awaddr_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [1:0]   awburst_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [3:0]   awcache_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [3:0]   awid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [7:0]   awlen_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire           awlock_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [2:0]   awprot_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [2:0]   awsize_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire           awvalid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire           bready_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire           rready_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [63:0]  wdata_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire           wlast_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [7:0]   wstrb_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire           wvalid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s;
wire   [31:0]  araddr_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [1:0]   arburst_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [3:0]   arcache_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [3:0]   arid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [7:0]   arlen_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire           arlock_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [2:0]   arprot_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [2:0]   arsize_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire           arvalid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [31:0]  awaddr_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [1:0]   awburst_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [3:0]   awcache_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [3:0]   awid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [7:0]   awlen_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire           awlock_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [2:0]   awprot_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [2:0]   awsize_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire           awvalid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire           bready_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire           rready_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [31:0]  wdata_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire           wlast_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [3:0]   wstrb_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire           wvalid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s;
wire   [31:0]  aaddr_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire   [1:0]   aburst_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire   [3:0]   acache_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire   [3:0]   aid_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire   [7:0]   alen_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire           alock_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire   [2:0]   aprot_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire   [3:0]   aregion_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire   [2:0]   asize_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire           avalid_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire           awrite_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire           dready_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire   [31:0]  wdata_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire           wlast_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire   [3:0]   wstrb_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire           wvalid_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s;
wire           arready_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire           awready_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [2:0]   bid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [1:0]   bresp_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire           bvalid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [63:0]  rdata_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [2:0]   rid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire           rlast_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [1:0]   rresp_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire           rvalid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire           wready_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s;
wire   [61:0]  a_data_perip0_gp_apb4_ib_int_async;
wire   [61:0]  a_data_perip1_gp_apb4_ib_int_async;
wire   [61:0]  a_data_sys_gp_apb4_ib_int_async;
wire   [1:0]   a_wpntr_gry_perip0_gp_apb4_ib_int_async;
wire   [1:0]   a_wpntr_gry_perip1_gp_apb4_ib_int_async;
wire   [1:0]   a_wpntr_gry_sys_gp_apb4_ib_int_async;
wire   [60:0]  ar_data_psram_slv_axi4_ib_int_async;
wire   [60:0]  ar_data_sdram_slv_axi4_ib_int_async;
wire           ar_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   ar_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   ar_wpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   ar_wpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [31:0]  araddr_vgalcd_mst_axi4;
wire   [1:0]   arburst_vgalcd_mst_axi4;
wire   [3:0]   arcache_vgalcd_mst_axi4;
wire   [2:0]   arid_vgalcd_mst_axi4;
wire   [7:0]   arlen_vgalcd_mst_axi4;
wire           arlock_vgalcd_mst_axi4;
wire   [2:0]   arprot_vgalcd_mst_axi4;
wire           arready_psram_slv_axi4;
wire           arready_sdram_slv_axi4;
wire   [2:0]   arsize_vgalcd_mst_axi4;
wire           arvalid_vgalcd_mst_axi4;
wire   [60:0]  aw_data_psram_slv_axi4_ib_int_async;
wire   [60:0]  aw_data_sdram_slv_axi4_ib_int_async;
wire           aw_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   aw_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   aw_wpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   aw_wpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [31:0]  awaddr_vgalcd_mst_axi4;
wire   [1:0]   awburst_vgalcd_mst_axi4;
wire   [3:0]   awcache_vgalcd_mst_axi4;
wire   [2:0]   awid_vgalcd_mst_axi4;
wire   [7:0]   awlen_vgalcd_mst_axi4;
wire           awlock_vgalcd_mst_axi4;
wire   [2:0]   awprot_vgalcd_mst_axi4;
wire           awready_psram_slv_axi4;
wire           awready_sdram_slv_axi4;
wire   [2:0]   awsize_vgalcd_mst_axi4;
wire           awvalid_vgalcd_mst_axi4;
wire   [4:0]   b_data_vgalcd_mst_axi4_ib_int_async;
wire           b_rpntr_bin_psram_slv_axi4_ib_int_async;
wire           b_rpntr_bin_sdram_slv_axi4_ib_int_async;
wire   [1:0]   b_rpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   b_rpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [1:0]   b_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [3:0]   bid_psram_slv_axi4;
wire   [3:0]   bid_sdram_slv_axi4;
wire           bready_vgalcd_mst_axi4;
wire   [1:0]   bresp_psram_slv_axi4;
wire   [1:0]   bresp_sdram_slv_axi4;
wire           bvalid_psram_slv_axi4;
wire           bvalid_sdram_slv_axi4;
wire           clk_peri_100mclk;
wire           clk_peri_100mclken;
wire           clk_peri_100mresetn;
wire           d_rpntr_bin_perip0_gp_apb4_ib_int_async;
wire           d_rpntr_bin_perip1_gp_apb4_ib_int_async;
wire           d_rpntr_bin_sys_gp_apb4_ib_int_async;
wire   [1:0]   d_rpntr_gry_perip0_gp_apb4_ib_int_async;
wire   [1:0]   d_rpntr_gry_perip1_gp_apb4_ib_int_async;
wire   [1:0]   d_rpntr_gry_sys_gp_apb4_ib_int_async;
wire   [31:0]  prdata_archinfo_slv_apb4;
wire   [31:0]  prdata_clint_slv_apb4;
wire   [31:0]  prdata_crc_slv_apb4;
wire   [31:0]  prdata_gpio_slv_apb4;
wire   [31:0]  prdata_i2c_slv_apb4;
wire   [31:0]  prdata_plic_slv_apb4;
wire   [31:0]  prdata_ps2_slv_apb4;
wire   [31:0]  prdata_psram_slv_apb4;
wire   [31:0]  prdata_pwm0_slv_apb4;
wire   [31:0]  prdata_pwm1_slv_apb4;
wire   [31:0]  prdata_pwm2_slv_apb4;
wire   [31:0]  prdata_qspi_slv_apb4;
wire   [31:0]  prdata_rcu_slv_apb4;
wire   [31:0]  prdata_rng_slv_apb4;
wire   [31:0]  prdata_rtc_slv_apb4;
wire   [31:0]  prdata_spi0_slv_apb4;
wire   [31:0]  prdata_spi1_slv_apb4;
wire   [31:0]  prdata_tim0_slv_apb4;
wire   [31:0]  prdata_tim1_slv_apb4;
wire   [31:0]  prdata_tim2_slv_apb4;
wire   [31:0]  prdata_tim3_slv_apb4;
wire   [31:0]  prdata_uart_slv_apb4;
wire   [31:0]  prdata_vgalcd_slv_apb4;
wire   [31:0]  prdata_wdg_slv_apb4;
wire           pready_archinfo_slv_apb4;
wire           pready_clint_slv_apb4;
wire           pready_crc_slv_apb4;
wire           pready_gpio_slv_apb4;
wire           pready_i2c_slv_apb4;
wire           pready_plic_slv_apb4;
wire           pready_ps2_slv_apb4;
wire           pready_psram_slv_apb4;
wire           pready_pwm0_slv_apb4;
wire           pready_pwm1_slv_apb4;
wire           pready_pwm2_slv_apb4;
wire           pready_qspi_slv_apb4;
wire           pready_rcu_slv_apb4;
wire           pready_rng_slv_apb4;
wire           pready_rtc_slv_apb4;
wire           pready_spi0_slv_apb4;
wire           pready_spi1_slv_apb4;
wire           pready_tim0_slv_apb4;
wire           pready_tim1_slv_apb4;
wire           pready_tim2_slv_apb4;
wire           pready_tim3_slv_apb4;
wire           pready_uart_slv_apb4;
wire           pready_vgalcd_slv_apb4;
wire           pready_wdg_slv_apb4;
wire           pslverr_archinfo_slv_apb4;
wire           pslverr_clint_slv_apb4;
wire           pslverr_crc_slv_apb4;
wire           pslverr_gpio_slv_apb4;
wire           pslverr_i2c_slv_apb4;
wire           pslverr_plic_slv_apb4;
wire           pslverr_ps2_slv_apb4;
wire           pslverr_psram_slv_apb4;
wire           pslverr_pwm0_slv_apb4;
wire           pslverr_pwm1_slv_apb4;
wire           pslverr_pwm2_slv_apb4;
wire           pslverr_qspi_slv_apb4;
wire           pslverr_rcu_slv_apb4;
wire           pslverr_rng_slv_apb4;
wire           pslverr_rtc_slv_apb4;
wire           pslverr_spi0_slv_apb4;
wire           pslverr_spi1_slv_apb4;
wire           pslverr_tim0_slv_apb4;
wire           pslverr_tim1_slv_apb4;
wire           pslverr_tim2_slv_apb4;
wire           pslverr_tim3_slv_apb4;
wire           pslverr_uart_slv_apb4;
wire           pslverr_vgalcd_slv_apb4;
wire           pslverr_wdg_slv_apb4;
wire   [71:0]  r_data_vgalcd_mst_axi4_ib_int_async;
wire           r_rpntr_bin_psram_slv_axi4_ib_int_async;
wire           r_rpntr_bin_sdram_slv_axi4_ib_int_async;
wire   [1:0]   r_rpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   r_rpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [1:0]   r_wpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [63:0]  rdata_psram_slv_axi4;
wire   [31:0]  rdata_sdram_slv_axi4;
wire   [3:0]   rid_psram_slv_axi4;
wire   [3:0]   rid_sdram_slv_axi4;
wire           rlast_psram_slv_axi4;
wire           rlast_sdram_slv_axi4;
wire           rready_vgalcd_mst_axi4;
wire   [1:0]   rresp_psram_slv_axi4;
wire   [1:0]   rresp_sdram_slv_axi4;
wire           rvalid_psram_slv_axi4;
wire           rvalid_sdram_slv_axi4;
wire   [36:0]  w_data_perip0_gp_apb4_ib_int_async;
wire   [36:0]  w_data_perip1_gp_apb4_ib_int_async;
wire   [72:0]  w_data_psram_slv_axi4_ib_int_async;
wire   [36:0]  w_data_sdram_slv_axi4_ib_int_async;
wire   [36:0]  w_data_sys_gp_apb4_ib_int_async;
wire           w_rpntr_bin_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   w_rpntr_gry_vgalcd_mst_axi4_ib_int_async;
wire   [1:0]   w_wpntr_gry_perip0_gp_apb4_ib_int_async;
wire   [1:0]   w_wpntr_gry_perip1_gp_apb4_ib_int_async;
wire   [1:0]   w_wpntr_gry_psram_slv_axi4_ib_int_async;
wire   [1:0]   w_wpntr_gry_sdram_slv_axi4_ib_int_async;
wire   [1:0]   w_wpntr_gry_sys_gp_apb4_ib_int_async;
wire   [63:0]  wdata_vgalcd_mst_axi4;
wire           wlast_vgalcd_mst_axi4;
wire           wready_psram_slv_axi4;
wire           wready_sdram_slv_axi4;
wire   [7:0]   wstrb_vgalcd_mst_axi4;
wire           wvalid_vgalcd_mst_axi4;



//-----------------------------------------------------------------------------
// Sub-Modules Instantiation
//-----------------------------------------------------------------------------

nic400_amib_perip0_gp_apb4_ysyx_rv32     u_amib_perip0_gp_apb4 (
  .paddr_gpio_slv_apb4  (paddr_gpio_slv_apb4),
  .pwdata_gpio_slv_apb4 (pwdata_gpio_slv_apb4),
  .pwrite_gpio_slv_apb4 (pwrite_gpio_slv_apb4),
  .pprot_gpio_slv_apb4  (pprot_gpio_slv_apb4),
  .pstrb_gpio_slv_apb4  (pstrb_gpio_slv_apb4),
  .penable_gpio_slv_apb4 (penable_gpio_slv_apb4),
  .psel_gpio_slv_apb4   (pselx_gpio_slv_apb4),
  .prdata_gpio_slv_apb4 (prdata_gpio_slv_apb4),
  .pslverr_gpio_slv_apb4 (pslverr_gpio_slv_apb4),
  .pready_gpio_slv_apb4 (pready_gpio_slv_apb4),
  .paddr_i2c_slv_apb4   (paddr_i2c_slv_apb4),
  .pwdata_i2c_slv_apb4  (pwdata_i2c_slv_apb4),
  .pwrite_i2c_slv_apb4  (pwrite_i2c_slv_apb4),
  .pprot_i2c_slv_apb4   (pprot_i2c_slv_apb4),
  .pstrb_i2c_slv_apb4   (pstrb_i2c_slv_apb4),
  .penable_i2c_slv_apb4 (penable_i2c_slv_apb4),
  .psel_i2c_slv_apb4    (pselx_i2c_slv_apb4),
  .prdata_i2c_slv_apb4  (prdata_i2c_slv_apb4),
  .pslverr_i2c_slv_apb4 (pslverr_i2c_slv_apb4),
  .pready_i2c_slv_apb4  (pready_i2c_slv_apb4),
  .aid_perip0_gp_apb4_s (aid_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .aaddr_perip0_gp_apb4_s (aaddr_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .alen_perip0_gp_apb4_s (alen_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .asize_perip0_gp_apb4_s (asize_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .aburst_perip0_gp_apb4_s (aburst_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .alock_perip0_gp_apb4_s (alock_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .acache_perip0_gp_apb4_s (acache_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .aprot_perip0_gp_apb4_s (aprot_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .awrite_perip0_gp_apb4_s (awrite_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .avalid_perip0_gp_apb4_s (avalid_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .aregion_perip0_gp_apb4_s (aregion_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .aready_perip0_gp_apb4_s (aready_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .wdata_perip0_gp_apb4_s (wdata_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .wstrb_perip0_gp_apb4_s (wstrb_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .wlast_perip0_gp_apb4_s (wlast_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .wvalid_perip0_gp_apb4_s (wvalid_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .wready_perip0_gp_apb4_s (wready_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .did_perip0_gp_apb4_s (did_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .ddata_perip0_gp_apb4_s (ddata_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .dresp_perip0_gp_apb4_s (dresp_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .dlast_perip0_gp_apb4_s (dlast_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .dbnr_perip0_gp_apb4_s (dbnr_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .dvalid_perip0_gp_apb4_s (dvalid_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .dready_perip0_gp_apb4_s (dready_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .aclk                 (clk_peri_100mclk),
  .aresetn              (clk_peri_100mresetn),
  .paddr_pwm0_slv_apb4  (paddr_pwm0_slv_apb4),
  .pwdata_pwm0_slv_apb4 (pwdata_pwm0_slv_apb4),
  .pwrite_pwm0_slv_apb4 (pwrite_pwm0_slv_apb4),
  .pprot_pwm0_slv_apb4  (pprot_pwm0_slv_apb4),
  .pstrb_pwm0_slv_apb4  (pstrb_pwm0_slv_apb4),
  .penable_pwm0_slv_apb4 (penable_pwm0_slv_apb4),
  .psel_pwm0_slv_apb4   (pselx_pwm0_slv_apb4),
  .prdata_pwm0_slv_apb4 (prdata_pwm0_slv_apb4),
  .pslverr_pwm0_slv_apb4 (pslverr_pwm0_slv_apb4),
  .pready_pwm0_slv_apb4 (pready_pwm0_slv_apb4),
  .paddr_pwm1_slv_apb4  (paddr_pwm1_slv_apb4),
  .pwdata_pwm1_slv_apb4 (pwdata_pwm1_slv_apb4),
  .pwrite_pwm1_slv_apb4 (pwrite_pwm1_slv_apb4),
  .pprot_pwm1_slv_apb4  (pprot_pwm1_slv_apb4),
  .pstrb_pwm1_slv_apb4  (pstrb_pwm1_slv_apb4),
  .penable_pwm1_slv_apb4 (penable_pwm1_slv_apb4),
  .psel_pwm1_slv_apb4   (pselx_pwm1_slv_apb4),
  .prdata_pwm1_slv_apb4 (prdata_pwm1_slv_apb4),
  .pslverr_pwm1_slv_apb4 (pslverr_pwm1_slv_apb4),
  .pready_pwm1_slv_apb4 (pready_pwm1_slv_apb4),
  .paddr_pwm2_slv_apb4  (paddr_pwm2_slv_apb4),
  .pwdata_pwm2_slv_apb4 (pwdata_pwm2_slv_apb4),
  .pwrite_pwm2_slv_apb4 (pwrite_pwm2_slv_apb4),
  .pprot_pwm2_slv_apb4  (pprot_pwm2_slv_apb4),
  .pstrb_pwm2_slv_apb4  (pstrb_pwm2_slv_apb4),
  .penable_pwm2_slv_apb4 (penable_pwm2_slv_apb4),
  .psel_pwm2_slv_apb4   (pselx_pwm2_slv_apb4),
  .prdata_pwm2_slv_apb4 (prdata_pwm2_slv_apb4),
  .pslverr_pwm2_slv_apb4 (pslverr_pwm2_slv_apb4),
  .pready_pwm2_slv_apb4 (pready_pwm2_slv_apb4),
  .paddr_qspi_slv_apb4  (paddr_qspi_slv_apb4),
  .pwdata_qspi_slv_apb4 (pwdata_qspi_slv_apb4),
  .pwrite_qspi_slv_apb4 (pwrite_qspi_slv_apb4),
  .pprot_qspi_slv_apb4  (pprot_qspi_slv_apb4),
  .pstrb_qspi_slv_apb4  (pstrb_qspi_slv_apb4),
  .penable_qspi_slv_apb4 (penable_qspi_slv_apb4),
  .psel_qspi_slv_apb4   (pselx_qspi_slv_apb4),
  .prdata_qspi_slv_apb4 (prdata_qspi_slv_apb4),
  .pslverr_qspi_slv_apb4 (pslverr_qspi_slv_apb4),
  .pready_qspi_slv_apb4 (pready_qspi_slv_apb4),
  .paddr_rtc_slv_apb4   (paddr_rtc_slv_apb4),
  .pwdata_rtc_slv_apb4  (pwdata_rtc_slv_apb4),
  .pwrite_rtc_slv_apb4  (pwrite_rtc_slv_apb4),
  .pprot_rtc_slv_apb4   (pprot_rtc_slv_apb4),
  .pstrb_rtc_slv_apb4   (pstrb_rtc_slv_apb4),
  .penable_rtc_slv_apb4 (penable_rtc_slv_apb4),
  .psel_rtc_slv_apb4    (pselx_rtc_slv_apb4),
  .prdata_rtc_slv_apb4  (prdata_rtc_slv_apb4),
  .pslverr_rtc_slv_apb4 (pslverr_rtc_slv_apb4),
  .pready_rtc_slv_apb4  (pready_rtc_slv_apb4),
  .paddr_uart_slv_apb4  (paddr_uart_slv_apb4),
  .pwdata_uart_slv_apb4 (pwdata_uart_slv_apb4),
  .pwrite_uart_slv_apb4 (pwrite_uart_slv_apb4),
  .pprot_uart_slv_apb4  (pprot_uart_slv_apb4),
  .pstrb_uart_slv_apb4  (pstrb_uart_slv_apb4),
  .penable_uart_slv_apb4 (penable_uart_slv_apb4),
  .psel_uart_slv_apb4   (pselx_uart_slv_apb4),
  .prdata_uart_slv_apb4 (prdata_uart_slv_apb4),
  .pslverr_uart_slv_apb4 (pslverr_uart_slv_apb4),
  .pready_uart_slv_apb4 (pready_uart_slv_apb4),
  .paddr_vgalcd_slv_apb4 (paddr_vgalcd_slv_apb4),
  .pwdata_vgalcd_slv_apb4 (pwdata_vgalcd_slv_apb4),
  .pwrite_vgalcd_slv_apb4 (pwrite_vgalcd_slv_apb4),
  .pprot_vgalcd_slv_apb4 (pprot_vgalcd_slv_apb4),
  .pstrb_vgalcd_slv_apb4 (pstrb_vgalcd_slv_apb4),
  .penable_vgalcd_slv_apb4 (penable_vgalcd_slv_apb4),
  .psel_vgalcd_slv_apb4 (pselx_vgalcd_slv_apb4),
  .prdata_vgalcd_slv_apb4 (prdata_vgalcd_slv_apb4),
  .pslverr_vgalcd_slv_apb4 (pslverr_vgalcd_slv_apb4),
  .pready_vgalcd_slv_apb4 (pready_vgalcd_slv_apb4),
  .apb_pclken           (clk_peri_100mclken),
  .paddr_wdg_slv_apb4   (paddr_wdg_slv_apb4),
  .pwdata_wdg_slv_apb4  (pwdata_wdg_slv_apb4),
  .pwrite_wdg_slv_apb4  (pwrite_wdg_slv_apb4),
  .pprot_wdg_slv_apb4   (pprot_wdg_slv_apb4),
  .pstrb_wdg_slv_apb4   (pstrb_wdg_slv_apb4),
  .penable_wdg_slv_apb4 (penable_wdg_slv_apb4),
  .psel_wdg_slv_apb4    (pselx_wdg_slv_apb4),
  .prdata_wdg_slv_apb4  (prdata_wdg_slv_apb4),
  .pslverr_wdg_slv_apb4 (pslverr_wdg_slv_apb4),
  .pready_wdg_slv_apb4  (pready_wdg_slv_apb4)
);


nic400_amib_perip1_gp_apb4_ysyx_rv32     u_amib_perip1_gp_apb4 (
  .paddr_archinfo_slv_apb4 (paddr_archinfo_slv_apb4),
  .pwdata_archinfo_slv_apb4 (pwdata_archinfo_slv_apb4),
  .pwrite_archinfo_slv_apb4 (pwrite_archinfo_slv_apb4),
  .pprot_archinfo_slv_apb4 (pprot_archinfo_slv_apb4),
  .pstrb_archinfo_slv_apb4 (pstrb_archinfo_slv_apb4),
  .penable_archinfo_slv_apb4 (penable_archinfo_slv_apb4),
  .psel_archinfo_slv_apb4 (pselx_archinfo_slv_apb4),
  .prdata_archinfo_slv_apb4 (prdata_archinfo_slv_apb4),
  .pslverr_archinfo_slv_apb4 (pslverr_archinfo_slv_apb4),
  .pready_archinfo_slv_apb4 (pready_archinfo_slv_apb4),
  .paddr_crc_slv_apb4   (paddr_crc_slv_apb4),
  .pwdata_crc_slv_apb4  (pwdata_crc_slv_apb4),
  .pwrite_crc_slv_apb4  (pwrite_crc_slv_apb4),
  .pprot_crc_slv_apb4   (pprot_crc_slv_apb4),
  .pstrb_crc_slv_apb4   (pstrb_crc_slv_apb4),
  .penable_crc_slv_apb4 (penable_crc_slv_apb4),
  .psel_crc_slv_apb4    (pselx_crc_slv_apb4),
  .prdata_crc_slv_apb4  (prdata_crc_slv_apb4),
  .pslverr_crc_slv_apb4 (pslverr_crc_slv_apb4),
  .pready_crc_slv_apb4  (pready_crc_slv_apb4),
  .aid_perip1_gp_apb4_s (aid_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .aaddr_perip1_gp_apb4_s (aaddr_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .alen_perip1_gp_apb4_s (alen_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .asize_perip1_gp_apb4_s (asize_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .aburst_perip1_gp_apb4_s (aburst_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .alock_perip1_gp_apb4_s (alock_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .acache_perip1_gp_apb4_s (acache_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .aprot_perip1_gp_apb4_s (aprot_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .awrite_perip1_gp_apb4_s (awrite_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .avalid_perip1_gp_apb4_s (avalid_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .aregion_perip1_gp_apb4_s (aregion_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .aready_perip1_gp_apb4_s (aready_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .wdata_perip1_gp_apb4_s (wdata_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .wstrb_perip1_gp_apb4_s (wstrb_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .wlast_perip1_gp_apb4_s (wlast_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .wvalid_perip1_gp_apb4_s (wvalid_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .wready_perip1_gp_apb4_s (wready_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .did_perip1_gp_apb4_s (did_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .ddata_perip1_gp_apb4_s (ddata_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .dresp_perip1_gp_apb4_s (dresp_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .dlast_perip1_gp_apb4_s (dlast_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .dbnr_perip1_gp_apb4_s (dbnr_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .dvalid_perip1_gp_apb4_s (dvalid_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .dready_perip1_gp_apb4_s (dready_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .aclk                 (clk_peri_100mclk),
  .aresetn              (clk_peri_100mresetn),
  .paddr_ps2_slv_apb4   (paddr_ps2_slv_apb4),
  .pwdata_ps2_slv_apb4  (pwdata_ps2_slv_apb4),
  .pwrite_ps2_slv_apb4  (pwrite_ps2_slv_apb4),
  .pprot_ps2_slv_apb4   (pprot_ps2_slv_apb4),
  .pstrb_ps2_slv_apb4   (pstrb_ps2_slv_apb4),
  .penable_ps2_slv_apb4 (penable_ps2_slv_apb4),
  .psel_ps2_slv_apb4    (pselx_ps2_slv_apb4),
  .prdata_ps2_slv_apb4  (prdata_ps2_slv_apb4),
  .pslverr_ps2_slv_apb4 (pslverr_ps2_slv_apb4),
  .pready_ps2_slv_apb4  (pready_ps2_slv_apb4),
  .paddr_psram_slv_apb4 (paddr_psram_slv_apb4),
  .pwdata_psram_slv_apb4 (pwdata_psram_slv_apb4),
  .pwrite_psram_slv_apb4 (pwrite_psram_slv_apb4),
  .pprot_psram_slv_apb4 (pprot_psram_slv_apb4),
  .pstrb_psram_slv_apb4 (pstrb_psram_slv_apb4),
  .penable_psram_slv_apb4 (penable_psram_slv_apb4),
  .psel_psram_slv_apb4  (pselx_psram_slv_apb4),
  .prdata_psram_slv_apb4 (prdata_psram_slv_apb4),
  .pslverr_psram_slv_apb4 (pslverr_psram_slv_apb4),
  .pready_psram_slv_apb4 (pready_psram_slv_apb4),
  .apb_pclken           (clk_peri_100mclken),
  .paddr_rng_slv_apb4   (paddr_rng_slv_apb4),
  .pwdata_rng_slv_apb4  (pwdata_rng_slv_apb4),
  .pwrite_rng_slv_apb4  (pwrite_rng_slv_apb4),
  .pprot_rng_slv_apb4   (pprot_rng_slv_apb4),
  .pstrb_rng_slv_apb4   (pstrb_rng_slv_apb4),
  .penable_rng_slv_apb4 (penable_rng_slv_apb4),
  .psel_rng_slv_apb4    (pselx_rng_slv_apb4),
  .prdata_rng_slv_apb4  (prdata_rng_slv_apb4),
  .pslverr_rng_slv_apb4 (pslverr_rng_slv_apb4),
  .pready_rng_slv_apb4  (pready_rng_slv_apb4),
  .paddr_spi0_slv_apb4  (paddr_spi0_slv_apb4),
  .pwdata_spi0_slv_apb4 (pwdata_spi0_slv_apb4),
  .pwrite_spi0_slv_apb4 (pwrite_spi0_slv_apb4),
  .pprot_spi0_slv_apb4  (pprot_spi0_slv_apb4),
  .pstrb_spi0_slv_apb4  (pstrb_spi0_slv_apb4),
  .penable_spi0_slv_apb4 (penable_spi0_slv_apb4),
  .psel_spi0_slv_apb4   (pselx_spi0_slv_apb4),
  .prdata_spi0_slv_apb4 (prdata_spi0_slv_apb4),
  .pslverr_spi0_slv_apb4 (pslverr_spi0_slv_apb4),
  .pready_spi0_slv_apb4 (pready_spi0_slv_apb4),
  .paddr_spi1_slv_apb4  (paddr_spi1_slv_apb4),
  .pwdata_spi1_slv_apb4 (pwdata_spi1_slv_apb4),
  .pwrite_spi1_slv_apb4 (pwrite_spi1_slv_apb4),
  .pprot_spi1_slv_apb4  (pprot_spi1_slv_apb4),
  .pstrb_spi1_slv_apb4  (pstrb_spi1_slv_apb4),
  .penable_spi1_slv_apb4 (penable_spi1_slv_apb4),
  .psel_spi1_slv_apb4   (pselx_spi1_slv_apb4),
  .prdata_spi1_slv_apb4 (prdata_spi1_slv_apb4),
  .pslverr_spi1_slv_apb4 (pslverr_spi1_slv_apb4),
  .pready_spi1_slv_apb4 (pready_spi1_slv_apb4),
  .paddr_tim0_slv_apb4  (paddr_tim0_slv_apb4),
  .pwdata_tim0_slv_apb4 (pwdata_tim0_slv_apb4),
  .pwrite_tim0_slv_apb4 (pwrite_tim0_slv_apb4),
  .pprot_tim0_slv_apb4  (pprot_tim0_slv_apb4),
  .pstrb_tim0_slv_apb4  (pstrb_tim0_slv_apb4),
  .penable_tim0_slv_apb4 (penable_tim0_slv_apb4),
  .psel_tim0_slv_apb4   (pselx_tim0_slv_apb4),
  .prdata_tim0_slv_apb4 (prdata_tim0_slv_apb4),
  .pslverr_tim0_slv_apb4 (pslverr_tim0_slv_apb4),
  .pready_tim0_slv_apb4 (pready_tim0_slv_apb4),
  .paddr_tim1_slv_apb4  (paddr_tim1_slv_apb4),
  .pwdata_tim1_slv_apb4 (pwdata_tim1_slv_apb4),
  .pwrite_tim1_slv_apb4 (pwrite_tim1_slv_apb4),
  .pprot_tim1_slv_apb4  (pprot_tim1_slv_apb4),
  .pstrb_tim1_slv_apb4  (pstrb_tim1_slv_apb4),
  .penable_tim1_slv_apb4 (penable_tim1_slv_apb4),
  .psel_tim1_slv_apb4   (pselx_tim1_slv_apb4),
  .prdata_tim1_slv_apb4 (prdata_tim1_slv_apb4),
  .pslverr_tim1_slv_apb4 (pslverr_tim1_slv_apb4),
  .pready_tim1_slv_apb4 (pready_tim1_slv_apb4),
  .paddr_tim2_slv_apb4  (paddr_tim2_slv_apb4),
  .pwdata_tim2_slv_apb4 (pwdata_tim2_slv_apb4),
  .pwrite_tim2_slv_apb4 (pwrite_tim2_slv_apb4),
  .pprot_tim2_slv_apb4  (pprot_tim2_slv_apb4),
  .pstrb_tim2_slv_apb4  (pstrb_tim2_slv_apb4),
  .penable_tim2_slv_apb4 (penable_tim2_slv_apb4),
  .psel_tim2_slv_apb4   (pselx_tim2_slv_apb4),
  .prdata_tim2_slv_apb4 (prdata_tim2_slv_apb4),
  .pslverr_tim2_slv_apb4 (pslverr_tim2_slv_apb4),
  .pready_tim2_slv_apb4 (pready_tim2_slv_apb4),
  .paddr_tim3_slv_apb4  (paddr_tim3_slv_apb4),
  .pwdata_tim3_slv_apb4 (pwdata_tim3_slv_apb4),
  .pwrite_tim3_slv_apb4 (pwrite_tim3_slv_apb4),
  .pprot_tim3_slv_apb4  (pprot_tim3_slv_apb4),
  .pstrb_tim3_slv_apb4  (pstrb_tim3_slv_apb4),
  .penable_tim3_slv_apb4 (penable_tim3_slv_apb4),
  .psel_tim3_slv_apb4   (pselx_tim3_slv_apb4),
  .prdata_tim3_slv_apb4 (prdata_tim3_slv_apb4),
  .pslverr_tim3_slv_apb4 (pslverr_tim3_slv_apb4),
  .pready_tim3_slv_apb4 (pready_tim3_slv_apb4)
);


nic400_amib_psram_slv_axi4_ysyx_rv32     u_amib_psram_slv_axi4 (
  .awid_psram_slv_axi4_m (awid_psram_slv_axi4),
  .awaddr_psram_slv_axi4_m (awaddr_psram_slv_axi4),
  .awlen_psram_slv_axi4_m (awlen_psram_slv_axi4),
  .awsize_psram_slv_axi4_m (awsize_psram_slv_axi4),
  .awburst_psram_slv_axi4_m (awburst_psram_slv_axi4),
  .awlock_psram_slv_axi4_m (awlock_psram_slv_axi4),
  .awcache_psram_slv_axi4_m (awcache_psram_slv_axi4),
  .awprot_psram_slv_axi4_m (awprot_psram_slv_axi4),
  .awvalid_psram_slv_axi4_m (awvalid_psram_slv_axi4),
  .awready_psram_slv_axi4_m (awready_psram_slv_axi4),
  .wdata_psram_slv_axi4_m (wdata_psram_slv_axi4),
  .wstrb_psram_slv_axi4_m (wstrb_psram_slv_axi4),
  .wlast_psram_slv_axi4_m (wlast_psram_slv_axi4),
  .wvalid_psram_slv_axi4_m (wvalid_psram_slv_axi4),
  .wready_psram_slv_axi4_m (wready_psram_slv_axi4),
  .bid_psram_slv_axi4_m (bid_psram_slv_axi4),
  .bresp_psram_slv_axi4_m (bresp_psram_slv_axi4),
  .bvalid_psram_slv_axi4_m (bvalid_psram_slv_axi4),
  .bready_psram_slv_axi4_m (bready_psram_slv_axi4),
  .arid_psram_slv_axi4_m (arid_psram_slv_axi4),
  .araddr_psram_slv_axi4_m (araddr_psram_slv_axi4),
  .arlen_psram_slv_axi4_m (arlen_psram_slv_axi4),
  .arsize_psram_slv_axi4_m (arsize_psram_slv_axi4),
  .arburst_psram_slv_axi4_m (arburst_psram_slv_axi4),
  .arlock_psram_slv_axi4_m (arlock_psram_slv_axi4),
  .arcache_psram_slv_axi4_m (arcache_psram_slv_axi4),
  .arprot_psram_slv_axi4_m (arprot_psram_slv_axi4),
  .arvalid_psram_slv_axi4_m (arvalid_psram_slv_axi4),
  .arready_psram_slv_axi4_m (arready_psram_slv_axi4),
  .rid_psram_slv_axi4_m (rid_psram_slv_axi4),
  .rdata_psram_slv_axi4_m (rdata_psram_slv_axi4),
  .rresp_psram_slv_axi4_m (rresp_psram_slv_axi4),
  .rlast_psram_slv_axi4_m (rlast_psram_slv_axi4),
  .rvalid_psram_slv_axi4_m (rvalid_psram_slv_axi4),
  .rready_psram_slv_axi4_m (rready_psram_slv_axi4),
  .awid_psram_slv_axi4_s (awid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awaddr_psram_slv_axi4_s (awaddr_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awlen_psram_slv_axi4_s (awlen_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awsize_psram_slv_axi4_s (awsize_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awburst_psram_slv_axi4_s (awburst_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awlock_psram_slv_axi4_s (awlock_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awcache_psram_slv_axi4_s (awcache_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awprot_psram_slv_axi4_s (awprot_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awvalid_psram_slv_axi4_s (awvalid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awready_psram_slv_axi4_s (awready_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .wdata_psram_slv_axi4_s (wdata_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .wstrb_psram_slv_axi4_s (wstrb_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .wlast_psram_slv_axi4_s (wlast_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .wvalid_psram_slv_axi4_s (wvalid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .wready_psram_slv_axi4_s (wready_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .bid_psram_slv_axi4_s (bid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .bresp_psram_slv_axi4_s (bresp_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .bvalid_psram_slv_axi4_s (bvalid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .bready_psram_slv_axi4_s (bready_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arid_psram_slv_axi4_s (arid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .araddr_psram_slv_axi4_s (araddr_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arlen_psram_slv_axi4_s (arlen_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arsize_psram_slv_axi4_s (arsize_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arburst_psram_slv_axi4_s (arburst_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arlock_psram_slv_axi4_s (arlock_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arcache_psram_slv_axi4_s (arcache_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arprot_psram_slv_axi4_s (arprot_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arvalid_psram_slv_axi4_s (arvalid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arready_psram_slv_axi4_s (arready_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .rid_psram_slv_axi4_s (rid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .rdata_psram_slv_axi4_s (rdata_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .rresp_psram_slv_axi4_s (rresp_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .rlast_psram_slv_axi4_s (rlast_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .rvalid_psram_slv_axi4_s (rvalid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .rready_psram_slv_axi4_s (rready_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .aclk                 (clk_peri_100mclk),
  .aresetn              (clk_peri_100mresetn)
);


nic400_amib_sdram_slv_axi4_ysyx_rv32     u_amib_sdram_slv_axi4 (
  .awid_nic400_axi4_sdram_s (awid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awaddr_nic400_axi4_sdram_s (awaddr_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awlen_nic400_axi4_sdram_s (awlen_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awsize_nic400_axi4_sdram_s (awsize_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awburst_nic400_axi4_sdram_s (awburst_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awlock_nic400_axi4_sdram_s (awlock_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awcache_nic400_axi4_sdram_s (awcache_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awprot_nic400_axi4_sdram_s (awprot_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awvalid_nic400_axi4_sdram_s (awvalid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awready_nic400_axi4_sdram_s (awready_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .wdata_nic400_axi4_sdram_s (wdata_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .wstrb_nic400_axi4_sdram_s (wstrb_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .wlast_nic400_axi4_sdram_s (wlast_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .wvalid_nic400_axi4_sdram_s (wvalid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .wready_nic400_axi4_sdram_s (wready_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .bid_nic400_axi4_sdram_s (bid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .bresp_nic400_axi4_sdram_s (bresp_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .bvalid_nic400_axi4_sdram_s (bvalid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .bready_nic400_axi4_sdram_s (bready_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arid_nic400_axi4_sdram_s (arid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .araddr_nic400_axi4_sdram_s (araddr_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arlen_nic400_axi4_sdram_s (arlen_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arsize_nic400_axi4_sdram_s (arsize_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arburst_nic400_axi4_sdram_s (arburst_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arlock_nic400_axi4_sdram_s (arlock_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arcache_nic400_axi4_sdram_s (arcache_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arprot_nic400_axi4_sdram_s (arprot_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arvalid_nic400_axi4_sdram_s (arvalid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arready_nic400_axi4_sdram_s (arready_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .rid_nic400_axi4_sdram_s (rid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .rdata_nic400_axi4_sdram_s (rdata_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .rresp_nic400_axi4_sdram_s (rresp_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .rlast_nic400_axi4_sdram_s (rlast_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .rvalid_nic400_axi4_sdram_s (rvalid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .rready_nic400_axi4_sdram_s (rready_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .aclk                 (clk_peri_100mclk),
  .aresetn              (clk_peri_100mresetn),
  .awid_sdram_slv_axi4_m (awid_sdram_slv_axi4),
  .awaddr_sdram_slv_axi4_m (awaddr_sdram_slv_axi4),
  .awlen_sdram_slv_axi4_m (awlen_sdram_slv_axi4),
  .awsize_sdram_slv_axi4_m (awsize_sdram_slv_axi4),
  .awburst_sdram_slv_axi4_m (awburst_sdram_slv_axi4),
  .awlock_sdram_slv_axi4_m (awlock_sdram_slv_axi4),
  .awcache_sdram_slv_axi4_m (awcache_sdram_slv_axi4),
  .awprot_sdram_slv_axi4_m (awprot_sdram_slv_axi4),
  .awvalid_sdram_slv_axi4_m (awvalid_sdram_slv_axi4),
  .awready_sdram_slv_axi4_m (awready_sdram_slv_axi4),
  .wdata_sdram_slv_axi4_m (wdata_sdram_slv_axi4),
  .wstrb_sdram_slv_axi4_m (wstrb_sdram_slv_axi4),
  .wlast_sdram_slv_axi4_m (wlast_sdram_slv_axi4),
  .wvalid_sdram_slv_axi4_m (wvalid_sdram_slv_axi4),
  .wready_sdram_slv_axi4_m (wready_sdram_slv_axi4),
  .bid_sdram_slv_axi4_m (bid_sdram_slv_axi4),
  .bresp_sdram_slv_axi4_m (bresp_sdram_slv_axi4),
  .bvalid_sdram_slv_axi4_m (bvalid_sdram_slv_axi4),
  .bready_sdram_slv_axi4_m (bready_sdram_slv_axi4),
  .arid_sdram_slv_axi4_m (arid_sdram_slv_axi4),
  .araddr_sdram_slv_axi4_m (araddr_sdram_slv_axi4),
  .arlen_sdram_slv_axi4_m (arlen_sdram_slv_axi4),
  .arsize_sdram_slv_axi4_m (arsize_sdram_slv_axi4),
  .arburst_sdram_slv_axi4_m (arburst_sdram_slv_axi4),
  .arlock_sdram_slv_axi4_m (arlock_sdram_slv_axi4),
  .arcache_sdram_slv_axi4_m (arcache_sdram_slv_axi4),
  .arprot_sdram_slv_axi4_m (arprot_sdram_slv_axi4),
  .arvalid_sdram_slv_axi4_m (arvalid_sdram_slv_axi4),
  .arready_sdram_slv_axi4_m (arready_sdram_slv_axi4),
  .rid_sdram_slv_axi4_m (rid_sdram_slv_axi4),
  .rdata_sdram_slv_axi4_m (rdata_sdram_slv_axi4),
  .rresp_sdram_slv_axi4_m (rresp_sdram_slv_axi4),
  .rlast_sdram_slv_axi4_m (rlast_sdram_slv_axi4),
  .rvalid_sdram_slv_axi4_m (rvalid_sdram_slv_axi4),
  .rready_sdram_slv_axi4_m (rready_sdram_slv_axi4)
);


nic400_amib_sys_gp_apb4_ysyx_rv32     u_amib_sys_gp_apb4 (
  .paddr_clint_slv_apb4 (paddr_clint_slv_apb4),
  .pwdata_clint_slv_apb4 (pwdata_clint_slv_apb4),
  .pwrite_clint_slv_apb4 (pwrite_clint_slv_apb4),
  .pprot_clint_slv_apb4 (pprot_clint_slv_apb4),
  .pstrb_clint_slv_apb4 (pstrb_clint_slv_apb4),
  .penable_clint_slv_apb4 (penable_clint_slv_apb4),
  .psel_clint_slv_apb4  (pselx_clint_slv_apb4),
  .prdata_clint_slv_apb4 (prdata_clint_slv_apb4),
  .pslverr_clint_slv_apb4 (pslverr_clint_slv_apb4),
  .pready_clint_slv_apb4 (pready_clint_slv_apb4),
  .paddr_plic_slv_apb4  (paddr_plic_slv_apb4),
  .pwdata_plic_slv_apb4 (pwdata_plic_slv_apb4),
  .pwrite_plic_slv_apb4 (pwrite_plic_slv_apb4),
  .pprot_plic_slv_apb4  (pprot_plic_slv_apb4),
  .pstrb_plic_slv_apb4  (pstrb_plic_slv_apb4),
  .penable_plic_slv_apb4 (penable_plic_slv_apb4),
  .psel_plic_slv_apb4   (pselx_plic_slv_apb4),
  .prdata_plic_slv_apb4 (prdata_plic_slv_apb4),
  .pslverr_plic_slv_apb4 (pslverr_plic_slv_apb4),
  .pready_plic_slv_apb4 (pready_plic_slv_apb4),
  .paddr_rcu_slv_apb4   (paddr_rcu_slv_apb4),
  .pwdata_rcu_slv_apb4  (pwdata_rcu_slv_apb4),
  .pwrite_rcu_slv_apb4  (pwrite_rcu_slv_apb4),
  .pprot_rcu_slv_apb4   (pprot_rcu_slv_apb4),
  .pstrb_rcu_slv_apb4   (pstrb_rcu_slv_apb4),
  .penable_rcu_slv_apb4 (penable_rcu_slv_apb4),
  .psel_rcu_slv_apb4    (pselx_rcu_slv_apb4),
  .prdata_rcu_slv_apb4  (prdata_rcu_slv_apb4),
  .pslverr_rcu_slv_apb4 (pslverr_rcu_slv_apb4),
  .pready_rcu_slv_apb4  (pready_rcu_slv_apb4),
  .apb_pclken           (clk_peri_100mclken),
  .aid_sys_gp_apb4_s    (aid_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .aaddr_sys_gp_apb4_s  (aaddr_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .alen_sys_gp_apb4_s   (alen_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .asize_sys_gp_apb4_s  (asize_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .aburst_sys_gp_apb4_s (aburst_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .alock_sys_gp_apb4_s  (alock_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .acache_sys_gp_apb4_s (acache_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .aprot_sys_gp_apb4_s  (aprot_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .awrite_sys_gp_apb4_s (awrite_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .avalid_sys_gp_apb4_s (avalid_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .aregion_sys_gp_apb4_s (aregion_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .aready_sys_gp_apb4_s (aready_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .wdata_sys_gp_apb4_s  (wdata_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .wstrb_sys_gp_apb4_s  (wstrb_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .wlast_sys_gp_apb4_s  (wlast_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .wvalid_sys_gp_apb4_s (wvalid_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .wready_sys_gp_apb4_s (wready_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .did_sys_gp_apb4_s    (did_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .ddata_sys_gp_apb4_s  (ddata_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .dresp_sys_gp_apb4_s  (dresp_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .dlast_sys_gp_apb4_s  (dlast_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .dbnr_sys_gp_apb4_s   (dbnr_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .dvalid_sys_gp_apb4_s (dvalid_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .dready_sys_gp_apb4_s (dready_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .aclk                 (clk_peri_100mclk),
  .aresetn              (clk_peri_100mresetn)
);


nic400_asib_vgalcd_mst_axi4_ysyx_rv32     u_asib_vgalcd_mst_axi4 (
  .awid_vgalcd_mst_axi4_m (awid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awaddr_vgalcd_mst_axi4_m (awaddr_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awlen_vgalcd_mst_axi4_m (awlen_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awsize_vgalcd_mst_axi4_m (awsize_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awburst_vgalcd_mst_axi4_m (awburst_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awlock_vgalcd_mst_axi4_m (awlock_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awcache_vgalcd_mst_axi4_m (awcache_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awprot_vgalcd_mst_axi4_m (awprot_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awvalid_vgalcd_mst_axi4_m (awvalid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awvalid_vect_vgalcd_mst_axi4_m (awvalid_vect_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awregion_vgalcd_mst_axi4_m (awregion_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awready_vgalcd_mst_axi4_m (awready_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .wdata_vgalcd_mst_axi4_m (wdata_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .wstrb_vgalcd_mst_axi4_m (wstrb_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .wlast_vgalcd_mst_axi4_m (wlast_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .wvalid_vgalcd_mst_axi4_m (wvalid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .wready_vgalcd_mst_axi4_m (wready_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .bid_vgalcd_mst_axi4_m (bid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .bresp_vgalcd_mst_axi4_m (bresp_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .bvalid_vgalcd_mst_axi4_m (bvalid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .bready_vgalcd_mst_axi4_m (bready_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arid_vgalcd_mst_axi4_m (arid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .araddr_vgalcd_mst_axi4_m (araddr_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arlen_vgalcd_mst_axi4_m (arlen_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arsize_vgalcd_mst_axi4_m (arsize_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arburst_vgalcd_mst_axi4_m (arburst_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arlock_vgalcd_mst_axi4_m (arlock_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arcache_vgalcd_mst_axi4_m (arcache_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arprot_vgalcd_mst_axi4_m (arprot_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arvalid_vgalcd_mst_axi4_m (arvalid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arvalid_vect_vgalcd_mst_axi4_m (arvalid_vect_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arregion_vgalcd_mst_axi4_m (arregion_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arready_vgalcd_mst_axi4_m (arready_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .rid_vgalcd_mst_axi4_m (rid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .rdata_vgalcd_mst_axi4_m (rdata_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .rresp_vgalcd_mst_axi4_m (rresp_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .rlast_vgalcd_mst_axi4_m (rlast_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .rvalid_vgalcd_mst_axi4_m (rvalid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .rready_vgalcd_mst_axi4_m (rready_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .aclk                 (clk_peri_100mclk),
  .aresetn              (clk_peri_100mresetn),
  .awid_vgalcd_mst_axi4_s (awid_vgalcd_mst_axi4),
  .awaddr_vgalcd_mst_axi4_s (awaddr_vgalcd_mst_axi4),
  .awlen_vgalcd_mst_axi4_s (awlen_vgalcd_mst_axi4),
  .awsize_vgalcd_mst_axi4_s (awsize_vgalcd_mst_axi4),
  .awburst_vgalcd_mst_axi4_s (awburst_vgalcd_mst_axi4),
  .awlock_vgalcd_mst_axi4_s (awlock_vgalcd_mst_axi4),
  .awcache_vgalcd_mst_axi4_s (awcache_vgalcd_mst_axi4),
  .awprot_vgalcd_mst_axi4_s (awprot_vgalcd_mst_axi4),
  .awvalid_vgalcd_mst_axi4_s (awvalid_vgalcd_mst_axi4),
  .awready_vgalcd_mst_axi4_s (awready_vgalcd_mst_axi4),
  .wdata_vgalcd_mst_axi4_s (wdata_vgalcd_mst_axi4),
  .wstrb_vgalcd_mst_axi4_s (wstrb_vgalcd_mst_axi4),
  .wlast_vgalcd_mst_axi4_s (wlast_vgalcd_mst_axi4),
  .wvalid_vgalcd_mst_axi4_s (wvalid_vgalcd_mst_axi4),
  .wready_vgalcd_mst_axi4_s (wready_vgalcd_mst_axi4),
  .bid_vgalcd_mst_axi4_s (bid_vgalcd_mst_axi4),
  .bresp_vgalcd_mst_axi4_s (bresp_vgalcd_mst_axi4),
  .bvalid_vgalcd_mst_axi4_s (bvalid_vgalcd_mst_axi4),
  .bready_vgalcd_mst_axi4_s (bready_vgalcd_mst_axi4),
  .arid_vgalcd_mst_axi4_s (arid_vgalcd_mst_axi4),
  .araddr_vgalcd_mst_axi4_s (araddr_vgalcd_mst_axi4),
  .arlen_vgalcd_mst_axi4_s (arlen_vgalcd_mst_axi4),
  .arsize_vgalcd_mst_axi4_s (arsize_vgalcd_mst_axi4),
  .arburst_vgalcd_mst_axi4_s (arburst_vgalcd_mst_axi4),
  .arlock_vgalcd_mst_axi4_s (arlock_vgalcd_mst_axi4),
  .arcache_vgalcd_mst_axi4_s (arcache_vgalcd_mst_axi4),
  .arprot_vgalcd_mst_axi4_s (arprot_vgalcd_mst_axi4),
  .arvalid_vgalcd_mst_axi4_s (arvalid_vgalcd_mst_axi4),
  .arready_vgalcd_mst_axi4_s (arready_vgalcd_mst_axi4),
  .rid_vgalcd_mst_axi4_s (rid_vgalcd_mst_axi4),
  .rdata_vgalcd_mst_axi4_s (rdata_vgalcd_mst_axi4),
  .rresp_vgalcd_mst_axi4_s (rresp_vgalcd_mst_axi4),
  .rlast_vgalcd_mst_axi4_s (rlast_vgalcd_mst_axi4),
  .rvalid_vgalcd_mst_axi4_s (rvalid_vgalcd_mst_axi4),
  .rready_vgalcd_mst_axi4_s (rready_vgalcd_mst_axi4)
);


nic400_ib_perip0_gp_apb4_ib_master_domain_ysyx_rv32     u_ib_perip0_gp_apb4_ib_m (
  .aid_itb_m            (aid_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .aaddr_itb_m          (aaddr_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .alen_itb_m           (alen_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .asize_itb_m          (asize_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .aburst_itb_m         (aburst_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .alock_itb_m          (alock_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .acache_itb_m         (acache_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .aprot_itb_m          (aprot_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .awrite_itb_m         (awrite_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .avalid_itb_m         (avalid_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .aregion_itb_m        (aregion_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .aready_itb_m         (aready_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .wdata_itb_m          (wdata_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .wstrb_itb_m          (wstrb_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .wlast_itb_m          (wlast_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .wvalid_itb_m         (wvalid_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .wready_itb_m         (wready_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .did_itb_m            (did_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .ddata_itb_m          (ddata_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .dresp_itb_m          (dresp_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .dlast_itb_m          (dlast_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .dbnr_itb_m           (dbnr_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .dvalid_itb_m         (dvalid_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .dready_itb_m         (dready_perip0_gp_apb4_ib_perip0_gp_apb4_perip0_gp_apb4_s),
  .aclk_m               (clk_peri_100mclk),
  .aresetn_m            (clk_peri_100mresetn),
  .a_data_async         (a_data_perip0_gp_apb4_ib_int_async),
  .a_rpntr_gry_async    (a_rpntr_gry_perip0_gp_apb4_ib_int_async),
  .a_rpntr_bin          (a_rpntr_bin_perip0_gp_apb4_ib_int_async),
  .a_wpntr_gry_async    (a_wpntr_gry_perip0_gp_apb4_ib_int_async),
  .d_data_async         (d_data_perip0_gp_apb4_ib_int_async),
  .d_rpntr_gry_async    (d_rpntr_gry_perip0_gp_apb4_ib_int_async),
  .d_rpntr_bin          (d_rpntr_bin_perip0_gp_apb4_ib_int_async),
  .d_wpntr_gry_async    (d_wpntr_gry_perip0_gp_apb4_ib_int_async),
  .w_data_async         (w_data_perip0_gp_apb4_ib_int_async),
  .w_rpntr_gry_async    (w_rpntr_gry_perip0_gp_apb4_ib_int_async),
  .w_rpntr_bin          (w_rpntr_bin_perip0_gp_apb4_ib_int_async),
  .w_wpntr_gry_async    (w_wpntr_gry_perip0_gp_apb4_ib_int_async)
);


nic400_ib_perip1_gp_apb4_ib_master_domain_ysyx_rv32     u_ib_perip1_gp_apb4_ib_m (
  .aid_itb_m            (aid_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .aaddr_itb_m          (aaddr_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .alen_itb_m           (alen_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .asize_itb_m          (asize_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .aburst_itb_m         (aburst_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .alock_itb_m          (alock_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .acache_itb_m         (acache_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .aprot_itb_m          (aprot_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .awrite_itb_m         (awrite_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .avalid_itb_m         (avalid_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .aregion_itb_m        (aregion_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .aready_itb_m         (aready_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .wdata_itb_m          (wdata_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .wstrb_itb_m          (wstrb_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .wlast_itb_m          (wlast_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .wvalid_itb_m         (wvalid_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .wready_itb_m         (wready_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .did_itb_m            (did_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .ddata_itb_m          (ddata_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .dresp_itb_m          (dresp_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .dlast_itb_m          (dlast_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .dbnr_itb_m           (dbnr_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .dvalid_itb_m         (dvalid_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .dready_itb_m         (dready_perip1_gp_apb4_ib_perip1_gp_apb4_perip1_gp_apb4_s),
  .aclk_m               (clk_peri_100mclk),
  .aresetn_m            (clk_peri_100mresetn),
  .a_data_async         (a_data_perip1_gp_apb4_ib_int_async),
  .a_rpntr_gry_async    (a_rpntr_gry_perip1_gp_apb4_ib_int_async),
  .a_rpntr_bin          (a_rpntr_bin_perip1_gp_apb4_ib_int_async),
  .a_wpntr_gry_async    (a_wpntr_gry_perip1_gp_apb4_ib_int_async),
  .d_data_async         (d_data_perip1_gp_apb4_ib_int_async),
  .d_rpntr_gry_async    (d_rpntr_gry_perip1_gp_apb4_ib_int_async),
  .d_rpntr_bin          (d_rpntr_bin_perip1_gp_apb4_ib_int_async),
  .d_wpntr_gry_async    (d_wpntr_gry_perip1_gp_apb4_ib_int_async),
  .w_data_async         (w_data_perip1_gp_apb4_ib_int_async),
  .w_rpntr_gry_async    (w_rpntr_gry_perip1_gp_apb4_ib_int_async),
  .w_rpntr_bin          (w_rpntr_bin_perip1_gp_apb4_ib_int_async),
  .w_wpntr_gry_async    (w_wpntr_gry_perip1_gp_apb4_ib_int_async)
);


nic400_ib_psram_slv_axi4_ib_master_domain_ysyx_rv32     u_ib_psram_slv_axi4_ib_m (
  .awid_axi4_m          (awid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awaddr_axi4_m        (awaddr_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awlen_axi4_m         (awlen_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awsize_axi4_m        (awsize_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awburst_axi4_m       (awburst_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awlock_axi4_m        (awlock_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awcache_axi4_m       (awcache_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awprot_axi4_m        (awprot_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awvalid_axi4_m       (awvalid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .awregion_axi4_m      (),
  .awready_axi4_m       (awready_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .wdata_axi4_m         (wdata_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .wstrb_axi4_m         (wstrb_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .wlast_axi4_m         (wlast_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .wvalid_axi4_m        (wvalid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .wready_axi4_m        (wready_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .bid_axi4_m           (bid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .bresp_axi4_m         (bresp_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .bvalid_axi4_m        (bvalid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .bready_axi4_m        (bready_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arid_axi4_m          (arid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .araddr_axi4_m        (araddr_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arlen_axi4_m         (arlen_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arsize_axi4_m        (arsize_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arburst_axi4_m       (arburst_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arlock_axi4_m        (arlock_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arcache_axi4_m       (arcache_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arprot_axi4_m        (arprot_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arvalid_axi4_m       (arvalid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .arregion_axi4_m      (),
  .arready_axi4_m       (arready_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .rid_axi4_m           (rid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .rdata_axi4_m         (rdata_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .rresp_axi4_m         (rresp_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .rlast_axi4_m         (rlast_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .rvalid_axi4_m        (rvalid_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .rready_axi4_m        (rready_psram_slv_axi4_ib_psram_slv_axi4_psram_slv_axi4_s),
  .aclk_m               (clk_peri_100mclk),
  .aresetn_m            (clk_peri_100mresetn),
  .aw_data_async        (aw_data_psram_slv_axi4_ib_int_async),
  .aw_rpntr_gry_async   (aw_rpntr_gry_psram_slv_axi4_ib_int_async),
  .aw_rpntr_bin         (aw_rpntr_bin_psram_slv_axi4_ib_int_async),
  .aw_wpntr_gry_async   (aw_wpntr_gry_psram_slv_axi4_ib_int_async),
  .b_data_async         (b_data_psram_slv_axi4_ib_int_async),
  .b_rpntr_gry_async    (b_rpntr_gry_psram_slv_axi4_ib_int_async),
  .b_rpntr_bin          (b_rpntr_bin_psram_slv_axi4_ib_int_async),
  .b_wpntr_gry_async    (b_wpntr_gry_psram_slv_axi4_ib_int_async),
  .ar_data_async        (ar_data_psram_slv_axi4_ib_int_async),
  .ar_rpntr_gry_async   (ar_rpntr_gry_psram_slv_axi4_ib_int_async),
  .ar_rpntr_bin         (ar_rpntr_bin_psram_slv_axi4_ib_int_async),
  .ar_wpntr_gry_async   (ar_wpntr_gry_psram_slv_axi4_ib_int_async),
  .r_data_async         (r_data_psram_slv_axi4_ib_int_async),
  .r_rpntr_gry_async    (r_rpntr_gry_psram_slv_axi4_ib_int_async),
  .r_rpntr_bin          (r_rpntr_bin_psram_slv_axi4_ib_int_async),
  .r_wpntr_gry_async    (r_wpntr_gry_psram_slv_axi4_ib_int_async),
  .w_data_async         (w_data_psram_slv_axi4_ib_int_async),
  .w_rpntr_gry_async    (w_rpntr_gry_psram_slv_axi4_ib_int_async),
  .w_rpntr_bin          (w_rpntr_bin_psram_slv_axi4_ib_int_async),
  .w_wpntr_gry_async    (w_wpntr_gry_psram_slv_axi4_ib_int_async)
);


nic400_ib_sdram_slv_axi4_ib_master_domain_ysyx_rv32     u_ib_sdram_slv_axi4_ib_m (
  .awid_axi4_m          (awid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awaddr_axi4_m        (awaddr_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awlen_axi4_m         (awlen_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awsize_axi4_m        (awsize_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awburst_axi4_m       (awburst_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awlock_axi4_m        (awlock_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awcache_axi4_m       (awcache_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awprot_axi4_m        (awprot_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awvalid_axi4_m       (awvalid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .awregion_axi4_m      (),
  .awready_axi4_m       (awready_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .wdata_axi4_m         (wdata_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .wstrb_axi4_m         (wstrb_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .wlast_axi4_m         (wlast_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .wvalid_axi4_m        (wvalid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .wready_axi4_m        (wready_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .bid_axi4_m           (bid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .bresp_axi4_m         (bresp_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .bvalid_axi4_m        (bvalid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .bready_axi4_m        (bready_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arid_axi4_m          (arid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .araddr_axi4_m        (araddr_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arlen_axi4_m         (arlen_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arsize_axi4_m        (arsize_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arburst_axi4_m       (arburst_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arlock_axi4_m        (arlock_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arcache_axi4_m       (arcache_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arprot_axi4_m        (arprot_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arvalid_axi4_m       (arvalid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .arregion_axi4_m      (),
  .arready_axi4_m       (arready_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .rid_axi4_m           (rid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .rdata_axi4_m         (rdata_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .rresp_axi4_m         (rresp_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .rlast_axi4_m         (rlast_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .rvalid_axi4_m        (rvalid_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .rready_axi4_m        (rready_sdram_slv_axi4_ib_sdram_slv_axi4_nic400_axi4_sdram_s),
  .aclk_m               (clk_peri_100mclk),
  .aresetn_m            (clk_peri_100mresetn),
  .aw_data_async        (aw_data_sdram_slv_axi4_ib_int_async),
  .aw_rpntr_gry_async   (aw_rpntr_gry_sdram_slv_axi4_ib_int_async),
  .aw_rpntr_bin         (aw_rpntr_bin_sdram_slv_axi4_ib_int_async),
  .aw_wpntr_gry_async   (aw_wpntr_gry_sdram_slv_axi4_ib_int_async),
  .b_data_async         (b_data_sdram_slv_axi4_ib_int_async),
  .b_rpntr_gry_async    (b_rpntr_gry_sdram_slv_axi4_ib_int_async),
  .b_rpntr_bin          (b_rpntr_bin_sdram_slv_axi4_ib_int_async),
  .b_wpntr_gry_async    (b_wpntr_gry_sdram_slv_axi4_ib_int_async),
  .ar_data_async        (ar_data_sdram_slv_axi4_ib_int_async),
  .ar_rpntr_gry_async   (ar_rpntr_gry_sdram_slv_axi4_ib_int_async),
  .ar_rpntr_bin         (ar_rpntr_bin_sdram_slv_axi4_ib_int_async),
  .ar_wpntr_gry_async   (ar_wpntr_gry_sdram_slv_axi4_ib_int_async),
  .r_data_async         (r_data_sdram_slv_axi4_ib_int_async),
  .r_rpntr_gry_async    (r_rpntr_gry_sdram_slv_axi4_ib_int_async),
  .r_rpntr_bin          (r_rpntr_bin_sdram_slv_axi4_ib_int_async),
  .r_wpntr_gry_async    (r_wpntr_gry_sdram_slv_axi4_ib_int_async),
  .w_data_async         (w_data_sdram_slv_axi4_ib_int_async),
  .w_rpntr_gry_async    (w_rpntr_gry_sdram_slv_axi4_ib_int_async),
  .w_rpntr_bin          (w_rpntr_bin_sdram_slv_axi4_ib_int_async),
  .w_wpntr_gry_async    (w_wpntr_gry_sdram_slv_axi4_ib_int_async)
);


nic400_ib_sys_gp_apb4_ib_master_domain_ysyx_rv32     u_ib_sys_gp_apb4_ib_m (
  .aid_itb_m            (aid_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .aaddr_itb_m          (aaddr_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .alen_itb_m           (alen_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .asize_itb_m          (asize_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .aburst_itb_m         (aburst_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .alock_itb_m          (alock_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .acache_itb_m         (acache_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .aprot_itb_m          (aprot_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .awrite_itb_m         (awrite_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .avalid_itb_m         (avalid_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .aregion_itb_m        (aregion_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .aready_itb_m         (aready_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .wdata_itb_m          (wdata_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .wstrb_itb_m          (wstrb_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .wlast_itb_m          (wlast_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .wvalid_itb_m         (wvalid_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .wready_itb_m         (wready_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .did_itb_m            (did_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .ddata_itb_m          (ddata_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .dresp_itb_m          (dresp_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .dlast_itb_m          (dlast_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .dbnr_itb_m           (dbnr_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .dvalid_itb_m         (dvalid_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .dready_itb_m         (dready_sys_gp_apb4_ib_sys_gp_apb4_sys_gp_apb4_s),
  .aclk_m               (clk_peri_100mclk),
  .aresetn_m            (clk_peri_100mresetn),
  .a_data_async         (a_data_sys_gp_apb4_ib_int_async),
  .a_rpntr_gry_async    (a_rpntr_gry_sys_gp_apb4_ib_int_async),
  .a_rpntr_bin          (a_rpntr_bin_sys_gp_apb4_ib_int_async),
  .a_wpntr_gry_async    (a_wpntr_gry_sys_gp_apb4_ib_int_async),
  .d_data_async         (d_data_sys_gp_apb4_ib_int_async),
  .d_rpntr_gry_async    (d_rpntr_gry_sys_gp_apb4_ib_int_async),
  .d_rpntr_bin          (d_rpntr_bin_sys_gp_apb4_ib_int_async),
  .d_wpntr_gry_async    (d_wpntr_gry_sys_gp_apb4_ib_int_async),
  .w_data_async         (w_data_sys_gp_apb4_ib_int_async),
  .w_rpntr_gry_async    (w_rpntr_gry_sys_gp_apb4_ib_int_async),
  .w_rpntr_bin          (w_rpntr_bin_sys_gp_apb4_ib_int_async),
  .w_wpntr_gry_async    (w_wpntr_gry_sys_gp_apb4_ib_int_async)
);


nic400_ib_vgalcd_mst_axi4_ib_slave_domain_ysyx_rv32     u_ib_vgalcd_mst_axi4_ib_s (
  .awid_axi4_s          (awid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awaddr_axi4_s        (awaddr_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awlen_axi4_s         (awlen_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awsize_axi4_s        (awsize_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awburst_axi4_s       (awburst_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awlock_axi4_s        (awlock_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awcache_axi4_s       (awcache_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awprot_axi4_s        (awprot_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awvalid_axi4_s       (awvalid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awvalid_vect_axi4_s  (awvalid_vect_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awregion_axi4_s      (awregion_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .awready_axi4_s       (awready_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .wdata_axi4_s         (wdata_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .wstrb_axi4_s         (wstrb_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .wlast_axi4_s         (wlast_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .wvalid_axi4_s        (wvalid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .wready_axi4_s        (wready_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .bid_axi4_s           (bid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .bresp_axi4_s         (bresp_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .bvalid_axi4_s        (bvalid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .bready_axi4_s        (bready_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arid_axi4_s          (arid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .araddr_axi4_s        (araddr_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arlen_axi4_s         (arlen_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arsize_axi4_s        (arsize_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arburst_axi4_s       (arburst_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arlock_axi4_s        (arlock_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arcache_axi4_s       (arcache_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arprot_axi4_s        (arprot_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arvalid_axi4_s       (arvalid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arvalid_vect_axi4_s  (arvalid_vect_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arregion_axi4_s      (arregion_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .arready_axi4_s       (arready_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .rid_axi4_s           (rid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .rdata_axi4_s         (rdata_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .rresp_axi4_s         (rresp_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .rlast_axi4_s         (rlast_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .rvalid_axi4_s        (rvalid_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .rready_axi4_s        (rready_vgalcd_mst_axi4_vgalcd_mst_axi4_ib_axi4_s),
  .aclk_s               (clk_peri_100mclk),
  .aresetn_s            (clk_peri_100mresetn),
  .aw_data_async        (aw_data_vgalcd_mst_axi4_ib_int_async),
  .aw_rpntr_gry_async   (aw_rpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .aw_rpntr_bin         (aw_rpntr_bin_vgalcd_mst_axi4_ib_int_async),
  .aw_wpntr_gry_async   (aw_wpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .b_data_async         (b_data_vgalcd_mst_axi4_ib_int_async),
  .b_rpntr_gry_async    (b_rpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .b_rpntr_bin          (b_rpntr_bin_vgalcd_mst_axi4_ib_int_async),
  .b_wpntr_gry_async    (b_wpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .ar_data_async        (ar_data_vgalcd_mst_axi4_ib_int_async),
  .ar_rpntr_gry_async   (ar_rpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .ar_rpntr_bin         (ar_rpntr_bin_vgalcd_mst_axi4_ib_int_async),
  .ar_wpntr_gry_async   (ar_wpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .r_data_async         (r_data_vgalcd_mst_axi4_ib_int_async),
  .r_rpntr_gry_async    (r_rpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .r_rpntr_bin          (r_rpntr_bin_vgalcd_mst_axi4_ib_int_async),
  .r_wpntr_gry_async    (r_wpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .w_data_async         (w_data_vgalcd_mst_axi4_ib_int_async),
  .w_rpntr_gry_async    (w_rpntr_gry_vgalcd_mst_axi4_ib_int_async),
  .w_rpntr_bin          (w_rpntr_bin_vgalcd_mst_axi4_ib_int_async),
  .w_wpntr_gry_async    (w_wpntr_gry_vgalcd_mst_axi4_ib_int_async)
);



endmodule
